Design Of Low-power Programmable Frequency Divider Based On 22nm CMOS Process

In recent years,with the rapid development of wireless communication systems,especially the continuous improvement of market demands such as Wi Fi and Bluetooth,the communication technology applied to the 2.4GHz frequency band has become a research hotspot.In a phase-locked loop(PLL)system,the frequency divider is a very important module,and it is the key to the PLL system to provide high-performance oscillatory signals while maintaining low power consumption and low phase noise.On the basis of fully investigating the principles and characteristics of various frequency dividers,this paper designs a 2.4～2.625 GHz low-power programmable frequency divider based on22 nm CMOS process.The frequency divider adopts the structure of the dual-mode frequency divider cascade the Pulse Swallow counter.The frequency division ratio is 4/5 frequency division,among which the flip-flop adopts a true single-phase clock(TSPC)structure with embedded logic gates to reduce power consumption;the P/S counter is designed with an asynchronous cascaded subtraction counter with synchronous logic setting,which reduces bit errors due to synchronous logic setting,asynchronous cascading can reduce the complexity and power consumption of circuit design,where the P counter is 4bit,and the S counter is 2bit,which realizes the continuous variable frequency division ratio of 36～67.This paper completes the circuit design,pre-simulation,layout design,post-simulation,tape-out and chip testing of the frequency divider.The test results show that under the power supply voltage of 1V,the frequency division range is 0.4～15GHz,the input sensitivity can reach-26 d Bm,and the frequency division of 36～67 can be achieved.When the input signal frequency is 2.4GHz and the circuit is divided by 40,the phase noise of output signal is-140.7d Bc/Hz@1k Hz,-160 d Bc/Hz@1MHz.The core circuit current of the frequency divider is about 1.9m A,and the core size of the chip is 297μm×124μm.Therefore,the programmable frequency divider designed in this paper has the advantages of wide operating frequency range,low power consumption and low noise.Not only can it be used in Wi Fi and Bluetooth systems,but also in chips such as GPS and 5G after a simple modification.