| As an important part of deep learning,convolutional neural networks are widely used in the field of image recognition.In recent years,with the development of deep learning technology,the accuracy of neural network recognition has gradually improved.However,the overly redundant parameters and the huge amount of computation make it difficult to port to mobile devices.As an emerging discipline,deep learning has the characteristics of strong intersection of software and hardware,but the current neural network optimization methods are basically unilateral strategies proposed for algorithms or hardware,and rarely unify the two and give full play to the advantages of the two.Therefore,how to learn from the strengths of all and obtain the optimal acceleration effect is of great significance to the practical application of neural networks.In order to better combine the advantages of the two part,The algorithm-hardware co-design method adopted in this thesis to optimizes the design from the per SBFPective of hardware adaptability of the algorithm and the ability of hardware to efficiently process the algorithm.In terms of designing algorithms,this thesis optimizes the traditional neural network thinning method,innovatively introduces cropping pre-operation,adopts clustering methods to aggregate similar convolutional kernels,and judges the contribution of convolutional parameters in each functional group according to the norm size of the parameters,so as to better filter and eliminate the parameters.In order to improve the fine-tuning method of the algorithm,this thesis also draws on the method of neural network distillation,and introduces the original network as the "teacher" network in the neural network distillation model into the fine-tuning system,and strives to make the Sparse network get more meaningful training in the improved fine-tuning process.In addition,in order to reduce the processing of irregular weight parameters in the hardware inference process,the neural network trim adopts a structured channel Sparse method,thereby ensuring the hardware adaptation of the algorithm.In terms of hardware design,in order to improve the efficiency of accelerator convolution operation,this thesis redistributes the arrangement rules of weights and image parameters in the physical memory of the hardware according to the principle of channel priority,and designs a supporting efficient convolution module,thereby greatly saving the cost of convolution operation.Secondly,pooled modules that support multiple modes have been designed,making the application pace of the accelerator more extensive.The Ultra96-V2 FPGA development board is used in this thesis as a hardware platform to test the neural network hardware acceleration system,at 200 MHz frequency,the peak computing performance of the system reaches 137.6 GOPS,which can infer 7～8 test set pictures of Image Net per second in the optimized VGG network,and its performance-to-power ratio reaches37.38GOPS/W.Compared with the latest design,it has certain performance advantages in terms of computing power and power consumption. |
