High-sensitivity GFSK Baseband Receiver Circuit Design For Low-power Bluetooth Chip

Bluetooth Low Energy(BLE)devices have a high market share in the Io T market due to their low complexity,low power consumption,and low cost.However,the working environment of BLE devices is complex,and there is often a problem of high demodulation bit error rate in the environment of large noise interference.Therefore,the in-depth study of the GFSK(Gaussian Frequency Shift Keying)demodulation algorithm used in the BLE receiver is of great significance for designing a highly sensitive GFSK demodulation circuit.Starting from the many challenges faced by BLE GFSK demodulation,this thesis designs a set of highly sensitive GFSK demodulation scheme based on the improved GFSK demodulation algorithm.The scheme is based on the low-IF receiver architecture,and has been optimized in digital down-conversion,phase differential operation,functional connection and decision sampling algorithm.This thesis proposes to use the range loop counter to control the three-round iterative decision algorithm,supplemented by signal filtering,symbol antiinterference to achieve high sensitivity performance of GFSK demodulation,and uses Matlab to simulate and model each key module,and gives the demodulation of the corresponding module result.This thesis further designs the GFSK demodulation circuit,and optimizes the circuit design for the problems of complex anti-image interference implementation,low accuracy of sine and cosine waves,and large storage space,so as to balance high demodulation performance and low implementation complexity.Based on the design of the high-sensitivity GFSK demodulation circuit,this thesis builds an FPGA verification platform,and performs verification and analysis on the demodulation performance and hardware resources.The verification results show that under the system clock of 8MHz,the highly sensitive GFSK demodulation module in the digital receiver can correctly demodulate the BLE uncoded data packet with SNR of 8.9d B,and the bit error rate is 0.1%,which meets the design requirements.