Adaptive Voltage And Frequency Scaling System Design Based On Two-level Timing Error Correction

With the rapid development of integrated circuits,low-power design is becoming more and more important.The Adaptive Voltage and Frequency Scaling(AVFS)can compress the timing margin reserved for traditional digital integrated circuit designs to obtain power gain.In-situ monitoring AVFS monitors the real critical path of the chip to achieve the highest gain,but there are still some design difficulties:(1)The timing monitoring unit has high cost and poor robustness;(2)The monitoring effectiveness is low;(3)The cost of timing error correction circuits is high;(4)There is a lack of system-level timing error correction methods with low cost,fast response,and little impact;(5)There is a lack of efficient cooperation between circuitlevel timing error correction methods and system-level timing error correction methods.Thus,an in-situ monitoring AVFS based on two-level timing error correction is proposed in this thesis,the main research contents are as follows:(1)A new timing monitoring unit that combines timing error monitoring and critical path activation monitoring is proposed,which ensures the effectiveness of critical path timing monitoring.(2)A flip-flop with error correction function is proposed,which can realize the current cycle error correction and provide stable and low-cost circuit-level timing error correction.(3)A wide-frequency adaptive clock circuit is proposed,which can detect the magnitude of violation to minimize system performance loss.It can be gated to reduce power consumption when clock stretching is not required.(4)The above technology is applied to a neural network accelerator,and the voltage and frequency adjustment control logic that efficiently combines circuit-level timing error correction and system-level timing error correction is used to construct an in-situ AVFS system based on two-level timing error correction under TSMC 28 nm process.The simulation results show that the chip can work under the wide voltage of 0.36V～0.9V.The AVFS technology can achieve 20.1%～65.3% power gain and 12.5%～364% frequency gain.The area cost is only 9%.In addition,the system can perform adaptive clock stretching under severe timing errors,which only causes 5.4% performance loss.Therefore,the technology proposed in this thesis can accurately monitor the timing information of the chip in a wide voltage range,and reduce the voltage to the theoretical minimum value to obtain power gain.