Accuracy-Configurable Low Latency Adder Design

Approximate Computing is an efficient low power design methodology for fault-tolerant applications,it sacrifices a limited accuracy in exchange for the considerable reduction of power and delay.However,the system’s requirement of the accuracy may vary over time and upon user requirements.Thus,it is necessarily to design accuracy configurable circuits to adjust the output quality dynamically.In this thesis,an Accuracy-configurable Low Latency Adder(ALLA)is design.The main work of this thesis includes the following points: 1.A new approximate addition logic based on the carry generation is designed,which uses the AND operation of input addends to simplify the accurate carry-in calculation logic,significantly reduce the critical path delay and power consumption of the adder with small computation error.2.Based on the approximate addition logic,a novel Accuracy-Configurable Full Adder(ACFA)is proposed.This design only introduces 2 extra transistors on the basis of the traditional mirror adder,can switch between the accurate and approximate mode to dynamically adjust the calculation accuracy.3.Based on the ACFA,the ALLA is designed and its detailed analysis,comparisons and real application test are conducted.The experiment results based on the SMIC 40 nm process indicate that under the operating condition of 1.1V supply voltage,100 MHz frequency,TT corner and 25℃,compared with the traditional 16-bit Ripple Carry Adder(RCA),the proposed 16-bit ALLA only introduces 5.92%extra area overhead and provides 25.11% energy savings,31.58% shorter critical path delay,at the cost of 0.07% mean relative error distance when the low 8-bit full adders are in the approximate mode.On the basis of the proposed adder,the Le Net-5 convolutional neural network accelerator is designed.Simulation results show that compared with the convolution array based on the accurate adder,the convolution array using the ALLA has better energy efficiency and smaller critical path delay.