Research And Design Of Ultra-high Speed Fully Parallel Analog-to-digital Converter

Analog-to-Digital Converter(ADC)is used to convert real-world analog signals into digital signals.It is a key module in mixed-signal systems and can be used in many fields such as communications,video,audio,and sensors.Ultra-high-speed,medium-resolution ADCs are widely used in wireless communication systems,ultra-wideband systems,radio astronomy and other fields.Therefore,the study of single-core ultra-high-speed,high-input bandwidth fully parallel ADCs is of great significance to related engineering fields..This paper firstly introduces the basic principles of ADCs,related performance indicators and the characteristics of commonly used ADC architectures,analyzes the key points and technical difficulties in the design of ultra-high-speed single-core fully parallel ADCs,and proposes a system architecture that adopts modularization and digital logic splicing,using pipelines The digital logic of thought,splicing low-precision fully parallel sub-ADCs into higher-precision ADCs.At the circuit level,a high-speed circuit module and an improved differential open-loop sample-and-hold circuit that meet the requirements of ultra-high-speed sampling rate are used.When the sampling frequency is 10GS/s and the input signal frequency is 4.961 GHz,the effective number of bits reaches more than 11 bits.Under the sampling frequency of 20GS/s,the effective number of output bits can reach more than 8 bits;An ultra-high-speed three-level dynamic latch comparator with an external offset correction circuit is designed.When the differential input is 0.2m V,the comparison time is 41.3ps,which meets the requirements of design accuracy and speed.The mean square error of the offset voltage after correction is 0.37 m V,and the offset The voltage is effectively corrected;Use high-speed ROM linear encoding circuit,and add spark code elimination circuit to reduce bit error rate.Finally,using the multi-layer nested splicing method,the 4bits sub-ADC is spliced into a6 bits ADC,and then the 6bits ADC is spliced into an 8bits ADC.This design is based on 40 nm CMOS process,and completes the circuit and layout design of10 GHz 8bits fully parallel ADC.The overall layout area is 0.98mm2.After post-simulation of the circuit,when the sampling frequency is 10GS/s and the input signal frequency is 3.242 GHz,the SNDR It is 41.68 d B,the SFDR is 50.4d B,the ENOB is 6.631 bits,and the total power consumption of the circuit is 0.79 W.