Research And Design Of High-speed Multi-channel Analog Multiplexer

The multiplexer circuit can multiplex multiple low-speed signals into a single high-speed signal,thereby improving the utilization of optical fibers in communication.The output signal of the analog multiplexer circuit is a multi-level baseband signal.Compared with the digital multiplexer circuit,the bandwidth of the fiber channel can be more fully utilized.With the rapid development of communication technology,the channel capacity required for signal transmission has greatly increased,and the requirements for the number of channels and working speed of the multiplexer are also increasing.Therefore,it is of far-reaching significance to study high-speed multi-channel analog multiplexers.This paper introduces the basic structure of the analog multiplexer circuit and the corresponding switching scheme,and introduces the quantitative indicators to measure the output performance.In the case of comprehensively considering the design indicators such as working speed,output accuracy and circuit scale,it is decided to adopt the technical scheme of the 32-8-4-1 half-tree multiplexing structure,and design the corresponding switching scheme,which can not only reduce the cost of The requirement of clock signal accuracy can also reduce the scale of the clock generation circuit,which is conducive to the rapid establishment of the signal;the gate voltage bootstrap switch is used to form a sample-and-hold circuit,and by optimizing the switch structure,the impact on the output accuracy of the overall circuit is reduced.,when the sampling rate is 250 MHz,the effective number of output bits of the sample and hold circuit reaches 17 bits;the NMOS switch is used to form a gate switch array,and the on-resistance of the switch is reduced by adjusting the size of the MOS tube.When the input differential signal swing of the multiplexer is At 200 m V,the on-resistance of the switch is less than 20.6;the slew rate boosting technology and parallel peaking technology are used in the design of the snubber circuit to ensure that the slew rate and bandwidth of the snubber circuit meet the design requirements;a true single-phase clock D flip-flop is used as the clock generation The basic module of the circuit,when the input clock signal is 8GHz,the clock generation circuit can complete the frequency division and phase shift of the input clock signal,and the edge of the output clock signal is about 10 ps,which can meet the switching speed requirements;a single-ended to differential circuit is designed,Convert the single-ended input signal to a differential signal,and reduce the number of input pads on the premise of ensuring signal accuracy.This subject uses 45 nm CMOS technology to complete the circuit design and layout drawing of the analog multiplexer.The input of the multiplexer is 16 I/Q channels,the input signal rate is250MS/s,the differential swing is 200 m V,and the output single-channel signal rate is 8GS/s.Postsimulation of the circuit: the overall circuit gain is 0.73,and the RMS error of the output signal is 1%of the output swing,which meets the design requirements.