Implementation Of 5G-NR Downlink Control Channel Technology Based On Vector Processor

The 5th Generation Mobile Communication System(5G),as a new generation mobile communication standard widely recognized by the international community,has been implemented and applied commercially.Compared with 4G network,it greatly enriches Internet services,making it possible to apply technologies such as cloud services and virtual reality.However,relatively,its network structure is more complicated,and the amount of data to be processed is also larger,so how to ensure the efficiency and stability of the system becomes a big challenge.In the 5G system,the physical layer is responsible for sending and receiving information,in which the physical downlink control channel,which is responsible for carrying Downlink Control Information,plays an important in resource scheduling and is an important guarantee for the smooth running of the entire 5G system.The first part of this thesis introduces the research background of the thesis,briefly summarizes the important role of physical downlink control channel,then explores the research status of physical downlink control channel in detail,and arrange the structure of this thesis.The second part of this thesis studies the overall architecture of the physical layer in 5G communication system,and analyzes the channel composition,frame structure and time-frequency resource structure of the physical layer under 5G standard.This thesis introduces some concepts related to PDCCH,such as downlink control information,control resource set and search space,etc.,which provide theoretical basis for the following research.The third part of this thesis studies the transmission process of PDCCH under 5G standard,and analyzes the technologies involved in the transmission process,such as DCI format alignment,CRC attachment,channel coding,rate matching,scrambling,channel modulation and resource mapping,which pave the way for the design and implementation of PDCCH receiver.The fourth part of this thesis analyzes the receiving process of the physical downlink control channel,simulates the channel estimation and channel equalization algorithms in the receiving process,and analyzes the performance of different algorithms.The combination of least square algorithm and Wiener interpolation algorithm is proposed as the implementation scheme of channel estimation module,and the minimum mean square error equalization algorithm is used as the implementation scheme of channel equalization module,which achieves the balance between algorithm complexity and data processing performance.This thesis researches the blind detection scheme of the physical downlink control channel,and analyzes and compares the performance and efficiency of several blind detection algorithms.The exhaustive blind detection algorithm is proposed as the implementation scheme of blind detection module to obtain the best detection success rate.The fifth part of this thesis introduces the development platform of this thesis: CEVA-XC4500 DSP processor.Based on this vector processor,this paper designs and implements the main modules in the PDCCH receiving process,such as demapping,channel estimation,channel equalization,descrambling and demodulation,by using Vec-C instruction set,and constructs the PDCCH receiving link.The functions of each module are simulated and tested,and the results are compared and tested with the floating-point simulation results based on MATLAB platform,and the running time of all modules is analyzed.The experimental results show that when the system bandwidth is 100 Mz,the subcarrier spacing is 30 KHz,the number of receiving antennas is 2,and the degree of aggregation is 4,the performance of the receiver is very small,and the total time consumption is 0.2402 ms,which is less than the duration of a single slot,meeting the design requirements.