Design And Research Of Hardened Latch With Multiple Node Upsets Tolerance In Integrated Circuits

With the continuous development of CMOS technology,the performance and integration of integrated circuits and systems have been improved to some extent,while the overhead has also been reduced.However,the reduction of transistor feature size makes the critical charge of the circuit decrease.The smaller the critical charge is,the more easily the logic value of the circuit node is affected by the external environment.Therefore,CMOS devices become more vulnerable to the impact of single event upset.Single event upset includes single event single node upset and single event multiple node upset,which will not cause permanent damage to devices and belongs to a kind of soft error.In deep submicron and nanotechnology,single event multiple node upset seriously affects the reliability of circuits.Its main difference from single event single node upset is that the logic values of multiple nodes change at the same time.Therefore,radiation hardened only for single node upset can no longer meet the requirements of aerospace applications with high reliability,so it is necessary to design a more reliable latch to ease the multiple node upset problem.In this thesis,aiming at the single event upset problem of integrated circuits in nano technology,based on the analysis and summary of existing latches,two kinds of quadruple node upset latch structures are designed:(1)Triple-modular-redundancy and Triple-level Error-interception based Quadruple Node Upsets Tolerant Latch(TTEQNUTL);(2)A Low-Cost Quadruple Node Upsets Self-Recoverable Latch(LCQNUSRL).The TTEQNUTL latch is connected by two C-elements and two clock-gating C-elements to form a storage module,which has the ability of self-recovery of single node upset.Based on the idea of triple modular redundancy,the storage module is copied three times,and the triple-level error interception module’s error interception ability makes the design latch can fully tolerate the quadruple node upset.HSPICE simulation results show that the latch increases area overhead by 26.58%,reduces power consumption by 29.13%,delays by 40.15%,and power delay product by58.96%.LCQNUSRL latch uses 24 C-elements to form a 6×4 array structure to build a fault-tolerant mechanism of four-stage filtering.The output of one column of C-elements acts as the input of the next column of C-elements,forming a feedback loop.When any four nodes of the latch flip over,the node with the correct logical value will recover the flipped node through the C-elements,realizing the quadruple node upset self-recovery.HSPICE simulation results show that the latch increases area overhead by 25%,reduces power consumption by 32.94%,delays by 30.2%,and power delay product by 53.35%.Figure [24] Table [8] Reference [45]...