Research On Hardware Architecture Of Versatile Video Coding Motion Estimation Based On FPGA

With the increasing requirements of consumer electronic products for real-time video transmission and video definition,encoders need to consume less resources to achieve higher compression performance and coding efficiency.Motion estimation is the core module of video coding,and the time consumed in the process of motion estimation accounts for more than 50% of the total coding time because of its high complexity and large amount of computation.In order to reduce the time consumption of motion estimation,reduce the computational complexity to reduce the consumption of resources,and achieve more fast and accurate motion estimation,a motion estimation algorithm based on search window partition is proposed,and a hardware architecture based on FPGA is designed.The specific research contents and work include:(1)The step size of the best matching block in the video sequence motion estimation module is counted and analyzed,and the law of the best matching block in the motion estimation is revealed.using the temporal and spatial correlation in the video information,the SAD value of the adjacent block and the appositive block is introduced to calculate the adaptive SAD threshold of the current pixel block,and the early termination of all search phases of motion estimation is judged,and the traditional early termination algorithm is optimized.(2)A motion estimation algorithm based on search window partition is proposed,which is suitable for hardware implementation.According to the arrangement law of the starting point of the square template search and the distribution law of the current block size in the motion estimation module,a block segmentation scheme and data reuse scheme based on 64 pixel search window and search starting point are proposed.reduce the amount of data that needs to be read and saved,and save storage resources.The experimental results show that the proposed algorithm reduces the motion estimation time by more than 94.82%,and the video quality is almost unchanged,and the BD-PSNR is less than-0.05.(3)According to the motion estimation algorithm based on search window partition proposed in this paper,the hardware architecture is designed,which can support the video transmission of 8K@60fps at most,and the RTL code design is realized based on Verilog HDL hardware description language.Through the design idea of time-sharing multiplexing and pipeline,the consumption of hardware resources is reduced and the data throughput is improved.The simulation results based on Modelsim verify the correctness of the hardware architecture.