Design And Implementation Of DDR Controller For Memory Test System

With the rapid development of integrated circuit test industry,the demand of memory chips is increasing day by day.In this context,most of the chips and memory testing equipment still rely on imports.It is urgent to promote the process of localization.The memory testing equipment can carry out comprehensive testing for the memory chips,but the function testing of the memory chips mainly depends on the controller.Therefore,the research on the controller of the memory test system is very important.Based on memory test system,DDR controller is designed in this paper.Custom test algorithm depends on how to use according to the rules of the instruction system.Users can edit instructions and configuration information on the upper computer interface according to the test requirements.The controller generates commands,address and data according to the received information.The signals output with different data rates not only meet DDR timing sequence but also realize programmable.It provides a solution for domestic DDR testing.The main research contents of this paper include:1.Overall scheme design: Analyzing the requirements of memory test system and DDR timing,DDR controller is divided into six parts including Sequence Controller,Algorithmic Pattern Generator,Programmable Data Selector,Data expansion module and Timing Generator.It is theoretically demonstrated that the instructions and configuration information are sent from the personal computer and the final data is sent to the correct channels.2.DDR controller design: DDR controller is designed based on Xilinx FPGA,which generates the original address and data according to the instructions and configuration information.Then,the desired signals are selected by the programmable data selector and sent to channels.3.Custom test waveforms: In order to generate the customized DDR high-speed signals,the low-speed parallel data generated inside FPGA is expanded by timing edge information,and finally converted into high-speed serial data through GTY high-speed transceiver series.4.Data synchronization among multiple modules: Since single FPGA can only generate 16 channels of test data,it can’t meet the requirements of DDR test,which puts forward higher requirements for the synchronization of multi-module data.Finally,data synchronization among multiple modules is realized from the perspective of multimodule synchronization trigger.Finally,several different types of instructions and corresponding configuration information are written,respectively producing different types of commands,address and data.The function of each module is verified on the board in the end.Besides,the generated test data is sent to Micron’s DDR model to verify that the generated test waveform meets expectations.