Hardware Design Of 10GSPS Data Acquisition And Storage Module

As a representative product of a data acquisition system,Digital Storage Oscilloscope is one of the necessary instruments in the electronic information industry.However,most domestic oscilloscopes have low indexes and narrow application ranges.This paper focuses on designing a domestic oscilloscope’s data acquisition system and achieving the maximum single-channel sampling rate of 10GSPS,2.5GHz bandwidth,8-bit vertical resolution,and 1Gpts storage depth index requirements.The main research contents of this thesis are as follows:1.Completes the construction of the hardware platform for the 10GSPS data acquisition system.According to the requirements of project indicators,this thesis firstly selects the type of key chips to be used in the data acquisition system such as ADC and FPGA,and secondly designs the circuit of key parts such as ADC driver and power supply module in the acquisition system,finally ensures these circuits work normally on the circuit board through reasonable PCB layout.2.Designs a Speed Reduction Processing and Error Correction Scheme for multiple ADC data receiving in FPGA.This thesis improves the existing multi-channel data synchronization scheme by researching the deceleration reception process of ADC data and proposes the multi-channel data synchronization correction method based on IDELAYE3 delay step accumulation,which has better stability and timing margin while ensuring ADC multiplex data synchronization.3.Designs a sampling data deep storage scheme around the DDR4 storage particles and MIG core with AXI4 Bus interface.By introducing the AXI4 protocol into the existing scheme,the data cross-clock processing process is simplified.At the same time,to accurately display the waveform of interest to users on the screen,this thesis studies the read and write process based on trigger control,completes the control of data read/write state switching and read/write address generation and then proposes a trigger address correction method based on shift registers,which implements the pinpoint of the trigger point during parallel storage of 10GSPS sampling data.4.Designed an extraction scheme for serial data points in parallel data streams.To solve the problem of excessive hardware resource consumption when implementing different extraction rates in multiple sampling rate modes in the existing scheme,this thesis achieves accurate extraction of serial data points in parallel sampling data by using the minimum number of basic extraction units and multi-level allocation of extraction rate.In addition,this thesis also reduces the loss of waveform information during high-capacity data extraction and improves the ability to capture burr signals through peak comparison in deep storage mode.Through the debugging of the hardware circuit and the performance test of the whole system,the acquisition system has the highest real-time sampling rate of 10GSPS,the actual analog bandwidth of 2.9GHz,and a storage depth of 1Gpts in the single channel mode.Also,the logic function has been successfully verified.