Study On Key Technologies For High Energy-Efficient Multicore VLIW Crypto-Processor

The integration of modern information and manufacturing technology,such as edge computing,virtual reality,and artificial intelligence,has led to a significant increase in the volume of network equipment.Edge devices will play an indispensable role in future network equipment as a medium for network access and information collection,as well as a vehicle for various intelligent applications.However,edge devices are located close to users,store sensitive privacy information,and have limited resources.Therefore,they have specific requirements such as high security,optimal performance,and low power consumption.A cipher processor is the vehicle of cipher algorithms and plays an essential role in protecting data security and privacy,as well as satisfying different security requirements.However,cryptographic algorithms are naturally computationally intensive,which conflicts with the energy consumption requirements of edge devices.Therefore,given the challenges of advancing power technology and the post-Moore era,designing energy-efficient cryptographic processors is of significant practical and research interest.This paper aims to tackle the challenge of designing cipher processors with high energy efficiency.Specifically,we investigate the possibility of utilizing multicore architectures to enhance the energy efficiency of existing VLIW cipher processors in our laboratory.To achieve the goal of energy-efficient cipher processors,this paper delves into three key aspects:energy efficiency models,scheduling control,and inter-core communication.We explore various levels of architecture,strategy,and design to optimize these aspects.Simulation analysis and board-level tests are conducted to validate the proposed approach for achieving a high energy-efficient multicore VLIW crypto-processor.This paper address the problem of determining the optimal core configuration and identifying the key factors that influence energy efficiency in multicore processors.We analyze the application of cryptographic tasks and the characteristics of single-core cryptographic processors to propose an energy efficiency model for multicore crypto-processors that extends Amdahl’s law.Based on MATLAB simulations,we find that the energy efficiency of multicore processors is significantly improved when the number of homogeneous cores matches the maximum degree of parallelism required for the cryptographic task at hand.The negative impact on energy efficiency is considerably reduced when the proportion of data preparation time is less than 10 percent.Frequency scaling affects energy efficiency.The smaller the idle/active energy ratio of the processor core,the larger the value of energy efficiency.The board-level tests conducted on the multicore crypto-processor chip confirm a strong correlation between the simulation results and actual measured data.The impact of various factors,such as preparation time,voltage frequency scaling,etc.,is found to be largely consistent with the simulation analysis,thus validating the effectiveness of the proposed energy efficiency model.This paper addresses the challenge of limiting energy efficiency improvement in multicore crypto-processors due to scheduling strategies.To overcome this limitation,we propose a multi-round mixed with single-round scheduling strategy based on the divisible loads theory.The MATLAB simulation analysis shows that the mixed scheduling approach performs better.The larger the transmission/computation time ratio of cryptographic tasks,the longer the workload completion time.The optimal load completion time and energy efficiency can be achieved when the number of processor cores and the number of scheduling rounds are appropriate values.Experimental results show that for different cryptographic algorithms,the proposed mixed scheduling strategy can shorten the load task completion time by 10.1%to 48.2%,and the corresponding energy efficiency value increases by 9.8%to 48.1%,effectively improving the processor energy efficiency.To further improve the energy efficiency of the processor by addressing inter-core communication mechanisms,this paper analyzes the requirements for inter-core communication in cryptographic tasks and proposes a hybrid inter-core communication method that balances performance and power consumption.The proposed hybrid inter-core communication method combines shared memory and message passing.Neighboring cores share memory,while distant cores transmit messages to balance performance and power consumption.Specifically,the shared memory circuit area is 18505.8μm~2 in CMOS 65nm technology,the average consumption of a single communication is 2.5 clock cycles,and the operating frequency is 714MHz.The circuit area of the routing node is 108717.1μm~2,the average consumption of a single communication is 3 clock cycles,and the operating frequency is 500MHz.The results of our experiment demonstrate that the proposed hybrid inter-core communication method achieves better energy efficiency.