Investigation Of Capacitance Characteristics Of SCR ESD Protection Devices On The High Voltage Process

Placing ESD(Electrostatic Discharge)protection devices on the IO port of an integrated circuit chip is an important measure to ensure the electrostatic reliability of the chip.For ESD devices used in high-speed chip signal ports,in addition to electrostatic windows and protection levels that meet circuit requirements,the impact of parasitic capacitance on chip high-speed signal transmission is also an important aspect that cannot be ignored.This paper first introduces the parasitic capacitance characteristics of common ESD protection devices,and then analyzes the electrostatic protection devices of LVTSCR(Low Voltage Trigger Silicon-Controlled Rectifier)and DDSCR(Dual-Direction Symmetrical Silicon-Controlled Rectifier)electrostatic protection devices.The parasitic capacitance characteristics of protection devices are studied,and the specific research contents are as follows:(1)Construction and analysis of the parasitic capacitance network of commonly used diodes,MOS tubes and SCR structure ESD devices.Through the analysis of the equivalent capacitance network of the conventional ESD device structure,it is concluded that the main factors affecting the size of the parasitic capacitance of the device are the size of the internal junction capacitance of the device and the coupling method of the junction capacitance.,the construction of the capacitor network and the simplified analysis process are given,which can provide guidance for the research on the capacitance characteristics of other types of thyristor electrostatic protection devices.(2)Research and optimization of parasitic capacitance characteristics of LVTSCR devices.A diode-embedded LVTSCR＿diode device is proposed,which reduces the capacitance due to the change of the parasitic capacitance network of the device due to the embedded diode.A LVTSCR＿electrode device is proposed to reduce the capacitance by changing the electrode connection method,and the reason for the reduction of the capacitance is the change of the parasitic capacitance network coupling method.A form of LVTSCR＿segment layout topology that optimizes overall device capacitance by reducing the size of the junction capacitances that make up the capacitance network by injecting region segments across two wells.The CV test shows that the parasitic capacitances of the three devices,LVTSCR＿diode,LVTSCR＿electrode,and LVTSCR＿segment,are reduced by 61%,32%,and 13%,respectively.(3)Research on parasitic capacitance characteristics of DDSCR devices.The paper discusses the influence and reasons of the lateral dimension,structure level,device finger length and guard ring of the DDSCR device on the parasitic capacitance of the device.The research results show that the increase of the critical dimension,the replacement of the P-EPI level with DHVNW and the increase of the finger length will increase the junction capacitance in the device capacitance network,thereby increasing the parasitic capacitance of the device.The capacitance remains unchanged;the parasitic capacitance of the DDSCR＿GR device with the guard ring is larger than that of the DDSCR device without the guard ring,because the guard ring introduces the parasitic capacitance between the N-type isolation ring and the P-type epitaxial layer,which is in parallel with the original capacitance of the device The change in the junction capacitance coupling relationship causes the difference in the parasitic capacitance of the device.