Design Of Ring Oscillator Based On Closed-loop Feedback

For emerging applications such as wearable devices,Internet of things,and wireless sensor networks,on-chip oscillator is considered a promising candidate to realize low-cost and low-power on-chip clock signal.Due to the inherent delay variations of the comparators and logic gates,oscillator generally suffers from inferior frequency stability at the output.In low-frequency designs,this effect is negligible if the delay is much smaller than the period of the oscillation signal.However,as the output frequency exceeds tens of megahertz,excessive power consumption is inevitable in the oscillator design to keep the delay within a reasonable range for desirable frequency stability.This paper firstly introduces the oscillation principle of oscillators according to the feedback and negative impedance theory,and then introduces three different structures of oscillators and their advantages and disadvantages.This paper studies and designs a closed-loop feedback ring oscillator circuit based on 0.18μm BCD process.In order to provide a stable power supply and reduce circuit power consumption,an LDO(Low Dropout Linear Regulator)is designed.a stable output voltage demands a exact reference voltage,so a reference voltage source is analyzed and designed first,and then an adaptive bias LDO is designed to maintain a good bandwidth at light and heavy loads.Through simulation verification,a stable output voltage of 2.5V can be obtained.After that,the whole structure and sub-circuit of the loop oscillator circuit based on closed-loop feedback are analyzed and designed,and the simulation verification is carried out.Through the temperature compensation of the resistance and frequency-locked loop technique is adopted,a very stable output frequency is obtained.Under the condition that the power supply voltage is 3～5.5V,the temperature variation range is-40～150℃,and five process angles are considered,the simulation results show that the output frequency variation range of the oscillator is kept within ±3%.The power consumption of the oscillator is 60μA at the output frequency of20MHz;the phase noise affects the purity of the output signal.It is obtained through simulation verification that the phase noise at the center frequency 1MHz offset frequency is-108 d Bc/Hz.Finally,the layout of the whole circuit is drawn and verified by post simulation.The comparison between the simulation results and the pre simulation also meets the requirements.