Research On Key Technologies Of 16-bit SAR ADC

With the rapid development of integrated circuit process,the computing speed of chips is increasing,and the area and power consumption are continuously decreasing.Digital circuits are widely used as the type of circuit that can directly benefit from process development.However,the signals prevalent in nature are analog signals that require an Analog-to-Digital Converter(ADC)to be converted to digital signals which can be processed by digital circuits.At the same time,precision instruments,healthcare,automotive electronics,and many other fields require the application of high-precision digital signals,leading to a rapidly increasing demand for high-precision ADCs.There are many types of ADCs,among which Successive Approximation Register(SAR)ADCs can combine the advantages of both digital and analog circuits and are more adaptable to process advances,thus becoming a hot research topic for scholars and enterprises.However,due to the influence of various non-ideal factors,the effective number of bits of SAR ADCs is limited to about 12 bits.To achieve higher accuracy,there are still many key technologies to break through.Therefore,this paper takes the study of key technologies of high precision SAR ADC as the core content,and designed a 16-bit high precision SAR ADC,the main research content includes:1.A design scheme of a multi-segmented capacitor array is proposed,which can solve the problem of exponentially increasing number of unit capacitors of chargeredistribution SAR ADC.Not only the two-segmented and the three-segmented capacitor array structures and calculation methods are obtained,but also the integersegmented or fractional-segmented forms can be selected,where the integer-segmented form reduces the difficulty of layout matching while reducing the area.Adopting this scheme,combined with the Vcm-based switching method,a low-power 16-bit segmented structure capacitor array is designed,which can reduce the overall area by99.4% and the average power consumption by 87.5% compared with the conventional structure.2.A self-calibration algorithm for differential structure is proposed,which can combine with the designed capacitor array structure to reduce the performance impact caused by capacitor mismatch.The algorithm improves the structure of the calibration DAC to make its maximum quantization range and minimum step adjustable;simplifies the quantization process of error voltages under differential structure,and improves the efficiency of calibration by using the method of cross-referencing the positive and negative terminals.The algorithm is verified by a behavioral-level model and the results show that the ENOB of the ADC is improved from 12.14 bits before calibration to 15.02 bits after calibration.3.A 16-bit 1 MS/s SAR ADC is designed based on 55 nm CMOS process,in which the S/H circuit adopts bottom-plate sampling and bootstrap switch;the capacitor array adopts the proposed differential segmented structure;the comparator is a cascade structure with three pre-amplification and latch stages,and the offset voltage selfcalibration technique is also adopted;the SAR control logic is asynchronous timing to improve the sampling rate.The circuit simulation results show that when the sampling rate reaches 1 MS/s,the SINAD of the SAR ADC is 82.44 d B,the SFDR is 83.75 d B,the THD is-83.18 d B,the ENOB is13.41 bits.