Design And Research Of High Performance Delta-Sigma ADC

Intelligent life has become the current goal pursued by people,and become the development trend of various devices in life,such as smart home,autonomous driving,etc.The intelligence of the device is also reflected in the corresponding operation of the external environment changes,perception of the external world can not be separated from the sensor,ADC as the necessary way to convert the physical information of the external environment into digital information that can be processed in the digital system,has been more and more scholars of research and development.Delta-Sigma ADC,a high-precision ADC with its unique technology of oversampling and noise shaping,has been widely researched and applied in the fields of sensors,precision measurement,high-quality audio,and other fields with low signal frequencies but high requirements for accuracy.This paper uses the VIS 0.18μm CMOS technology to design a Delta-Sigma ADC corresponding to an in-vehicle sensor using the current market advanced automotive electronics applications as a requirement.The current status of domestic and international research on Delta-Sigma ADC and the basis of its composition and structure are fully investigated,and the design specifications of the ADC are determined according to the current development needs of automotive electronics as an example.Secondly,using Simulink tool,we model and simulate the system of Delta-Sigma modulator with second-order cascaded integral feedforward(CIFF)structure selected in this paper,and optimize the comparative quantization process,and propose a multi-way quantization method,i.e.,by using the traditional one-bit quantization structure,without changing the structure,adding the combination of comparative quantization path and digital logic to achieve the two-bit quantization function.The quantization function is proposed.Through simulation,the quantization method proposed in this paper improves the signal-to-noise distortion ratio by 5.45%compared with the traditional one-bit quantization method,which can effectively improve the performance of Delta-Sigma modulator.Thirdly,the structural principle of the digital extraction filter is analyzed,and a graded downsampling filtering scheme is proposed,and the overall implementation of the digital extraction filter is given,which reduces the resource consumption by two-stage CIC filter and two-stage half-band filter with graded downsampling and CSD coding multiplication.After that,we use Verilog language to build the digital extraction filter in Delta-Sigma ADC and verify the timing logic and function simulation of the digital circuit by FPGA platform.Finally,the overall Delta-Sigma ADC structure is built and the mixed digital-to-analog simulation is completed,and the simulation results are analyzed.After simulation,the Delta-Sigma ADC designed in this paper has a sampling frequency of500KHz,an oversampling rate of 128,a passband cutoff frequency of 1.9KHz,an overall signal-to-noise distortion ratio of 85.2d B,an effective bit count of 13.9 bits,and a total power consumption of 578.6μW at a running clock of 1MHz and a supply voltage of 1.8V.And complete the analog and digital front-end and back-end full flow design summary,complete analog and digital circuit layout drawing,layout area of 0.7325mm~2.