A Low-power Low-noise Capacitive Readout Circuit For Accelerometers

With the rapid development of cloud computing technology in the Internet of things,sensors have become a hot topic.Among them,accelerometer is an inertial sensor that measures the acceleration of an object and is widely used in many fields.In particular,capacitive silicon micro accelerometers play an irreplaceable role in many fields due to their high accuracy,low power consumption,low noise,and easy integration.At the same time,under the application requirements of ultra-low power in mobile/wearable Internet of things,it is of great significance to design ultra-low power high-performance analog front-end circuits adapted to capacitive silicon micro accelerometers.With the rapid development of cloud computing technology in the Internet of things,sensors have become a hot topic.Among them,accelerometer is an inertial sensor that measures the acceleration of an object and is widely used in many fields.In particular,capacitive silicon micro accelerometers play an irreplaceable role in many fields due to their high accuracy,low power consumption,low noise,and easy integration.At the same time,under the application requirements of ultra-low power in mobile/wearable Internet of things,it is of great significance to design ultra-low power high-performance analog front-end circuits adapted to capacitive silicon micro accelerometers.This paper explores and designs a low-power,low-noise analog front-end integrated circuit of silicon micro accelerometer using SMIC 0.18μm CMOS technology,in accordance with current research status both domestically and internationally.The circuit consists of an operational amplifier and level shifter-based analog front-end core,and a gain control stage module.The analog front-end core utilizes a self-balancing bridge architecture with high linearity and no carrier driver to enable capacitive signal detection and voltage output conversion with low power consumption.Additionally,the circuit is designed with feedforward noise reduction technology and related double sampling technology to achieve low noise and high resolution.The voltage signal output of the self-balance-based analog front-end core is usually small,and the voltage signal can be amplified by the gain control stage to meet the maximum range input of the subsequent analog to digital converter.To further improve noise performance,correlated double sampling technique is used in the gain control stage to reduce the offset of the operational amplifier and the low frequency noise in the circuit.The simulation results indicate that when the gain control stage amplification is tripled,the analog front-end circuit can convert the accelerometer capacitance signal with a frequency of 100 Hz,a dynamic capacitance peak of 0.1p F,and a static capacitance of 1p F into the expected voltage signal with a total power consumption of265 n W.And the equivalent input noise is 45.11μV/ Hz@100Hz,which meets the design requirements of capacitor identification of 100 a F.This paper presents a silicon micro-accelerometer with an analog front-end circuit that boasts low power consumption,low noise and high resolution,making it a promising product for various markets.