FPGA Optimal Implementation Of State Secret Algorithm SM9

In recent years,based on the unique properties of bilinear pairwise encryption,it can be used to construct encryption protocols that other encryption algorithms cannot complete.Therefore,bilinear pairwise encryption has become a widely studied hot topic in asymmetric encryption systems.China officially released the commercial identification cipher algorithm SM9 based on bilinear pairs in 2016.However,compared to traditional public key cryptography schemes,the operation process of bilinear pairs is more complex.Currently,a considerable number of researchers have done a lot of work on the computational efficiency of bilinear pairs.In practical applications,there is still a certain gap in efficiency compared to traditional public key cryptography,So optimizing the calculation of bilinear pairs is still an important research topic.This thesis analyzes the signature part of the SM9 algorithm,and theoretically analyzes the more complex operations such as Optimal-ate pairs and higher power operations.Aiming at the special properties of the elements in Optimal-ate pairs after Miller cycles,a fast square algorithm based on circular subgroups is proposed,which reduces the number of multiplication in the base field by 50% compared to traditional square algorithms.Then,Karatsuba was used to optimize tower expansion operations,reducing the modular inverse of the twelfth expansion domain and the amount of base domain operations required for modular multiplication.Finally,NAF and Comb fixed base algorithms were used to optimize the final power and higher power,reducing the number of twelfth expansion domain operations and 67.45% base domain multiplication,respectively.In terms of hardware,the ASIP architecture based on FPGA implementation is used.When the basic computing unit is fixed,the ASIP architecture achieves complex logic control through microcode programming.Correspondingly,a custom RSIC instruction set is also designed,and the minimum operation units implemented in the instruction set are modular addition and subtraction,modular multiplication,and modular division units in the prime field.This thesis uses the Spinal HDL language to implement the corresponding ASIP architecture,and uses the Modelsim platform for simulation testing.The results are compared with the data of the SM9 standard use cases.Subsequently,a test was conducted on an Xlinx Artix-7 FPGA(XC7A50T-1FTG256C)board,and the waveform data was compared with the SM9 test document,verifying the completeness of the function.After synthesizing the project at a frequency of 167 Mhz,the resulting hardware resource cost for the single core version is 44360 LUT.The calculation of an Optimal-Ate pair once completed requires 194060 clock cycles,and the calculation of a high power operation requires 35023 clock cycles.In the multi-core version,the hardware resource overhead is 68697 LUT,calculating an Optimal-Ate pair requires 17337 clock cycles,and calculating a high power operation requires 2919 clock cycles.Compared with existing research,this paper has good comprehensive performance in terms of hardware resource consumption and computing speed.