A Novel RS-SPC Code Concatenation Decoding Algorithm And Hardware Implementation

Reed-Solomon（RS）codes have been widely used in data transmission and data storage due to their large transmission bandwidth,flexible coding rates,and capability to correct both random and burst errors.In addition to the continued research on new decoding algorithms for RS codes,the concatenated codes technique can also be used to further improve the error correction performance.Single parity check（SPC）codes,as the simple linear block codes,can form a concatenated structure with RS code.If making full use of the channel soft information to decode the SPC code,and evaluating the reliability of the symbols of the concatenated code by SPC codes,and then decoding the RS code,it is expected to obtain more excellent error correction performance and further expand the application field.In this thesis,based on the compiled code method of RS code and SPC code and the concatenated structure with SPC as the inner code and RS as the outer code,a new high-performance RS-SPC concatenated decoding algorithm is proposed,while an efficient hardware implementation is completed.Firstly,by making full use of the characteristics of SPC code,single parity check is performed to detect whether the SPC inner code is in error,and then the SPC decoding algorithm is designed using the characteristics of the received bit-level voltage,and the low-complexity Chase decoding based on the hard-decision decoding（HDD-LCC）algorithm is selected for RS decoding.In order to make full use of channel information and connect the two algorithms of inner and outer codes,the novel multiplicity assignment module is designed and integrated with the SPC decoding algorithm to process the received bit-level voltage to obtain the reliability of the concatenated code.The above scheme improves the decoding performance while increasing the efficiency and reducing the complexity of the decoding algorithm.Compared with the HDD-LCC and the current SPC（Kaneko）-RS（Chase）decoding algorithm using the same concatenated structure,the proposed algorithm can provide up to 1.78d B and 1.05d B of coding gain when bit-error rate is 10^-5.In the hardware design of the concatenated decoder,the focus is on reusing some similar circuit structures in the decoder to improve the hardware efficiency.This thesis uses Verilog HDL to build the concatenated decoder architecture and use Modelsim to make functional simulation and verification.In addition,the concatenated decoder is synthesized,static timing analysis（STA）and power analysis by Design Compiler and Prime Time PX with TSMC-90nm technology library.The normalized TSNT parameter of the proposed decoder is increased by 49.85%compared to the conventional HDD-LCC based RS decoder.