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Design And Implementation Of SpMV Accelerator Based On PIM Architecture

Posted on:2022-05-03Degree:MasterType:Thesis
Country:ChinaCandidate:S S YaoFull Text:PDF
GTID:2558307169477884Subject:Electronic Science and Technology
Abstract/Summary:PDF Full Text Request
Sparse Matrix Vector Multiplication SpMV(Sparse Matrix Vector Multiplication)has been widely used in many practical engineering problems,more representative applications include machine learning neural network diagram calculation and so on Such applications are usually there are a lot of SpMV operations,it brings a lot of calculation and to fetch overhead,the traditional computer architecture is adopted by the von neumann architecture is also calculate the design of the separation,this structure makes the bandwidth of the memory can’t keep up with the increasing CPU speed,leading to a decline in the overall performance In recent years,Processing In Memory(PIM),a newly emerged storage computing fusion architecture,can effectively alleviate this problem.The high bandwidth of PIM makes it possible to accelerate some Memory intensive applications,and SpMV is one of these applications Therefore,the design and implementation of SpMV accelerator based on PIM architecture has very important theoretical significance and application value.This paper is based on a High Bandwidth storage medium HBM(High Bandwidth)A scalable CPU-FPGA heterogeneous SpMV accelerator architecture is designed.The main work and innovations of this paper are as follows:1.Using the method of hardware and software co-design,the computing tasks of multiple PE devices are reasonably divided at the software level2.At the hardware level,an efficient scalable PE array is designed so that data can be continuously computed in PE.3.The structure of the exact multiplier inside PE is improved,and a parallel hybrid compression approximate multiplier is proposed to reduce the cost of hardware resources.Selection standards of sparse matrix test set for performance test and analysis,the results show that the proposed in this paper the PIM architectures can gain the highest average 19.54 times the performance of the acceleration,the characteristic and the sparse matrix of different scales,the acceleration effect also exists certain difference,from the perspective of the accelerating effect of the whole,the bigger the scale of the matrix,the higher the parallel degree of PE,the better the acceleration effect of SpMV accelerator.
Keywords/Search Tags:Sparse matrix vector multiplication, memory computation, heterogeneous structure, accelerator
PDF Full Text Request
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