Heterogeneous Chiplet Neural Network Accelerator Design For Edge Computing

With the rapid development of artificial intelligence,neural network models have been widely used in product recommendation,image segmentation,object recognition,voice recognition,and autonomous driving.In order to achieve higher accuracy,the number of layers of the neural network is constantly deepening,and with it is the rapid increase in the amount of neural network parameters and calculations.However,the performance development speed of traditional processors has lagged far behind the development speed of neural network models.The emergence of neural network special accelerators is to deal with the contradiction between processor performance and computing power requirements.One of the important reasons for the slow development of traditional processors is that the new technology has greatly reduced the product yield.For this reason,researchers have proposed chiplet technology to solve the problem of high design and manufacturing costs of chips under the new technology.The chiplet technology is to divide a large chip into multiple small components,and then package these small chips on the same interposer through advanced packaging technology to realize the interconnection between the chips.At the same time,the advanced packaging technology is also a convenient way for heterogeneous integration.In order to relieve the pressure of cloud server communication and computing to improve the service quality of edge devices,neural network accelerators are also introduced at the edge to achieve efficient edge computing.The proposal of the lightweight neural network basically maintains the accuracy of the model,while effectively reducing the amount of model parameters and calculations,making the edge computing of the neural network possible.Under the above background,we design a lightweight neural network accelerator for edge computing with fixed load.This accelerator adopts a design based on heterogeneous chiplets,which effectively improves the calculating efficiency of the lightweight neural network on the accelerator.The main work of the thesis includes:First,we propose a method for estimating the calculation cycles and energy consumption of a lightweight neural network model on a designated accelerator.We analyze the basic components of lightweight neural networks,and re-split part of the complex design of lightweight neural networks into these basic units.Then we try to scale and divide the load tasks of these lightweight neural networks on the input and output channels,run these loads on some of the existing neural network accelerators,and obtain the corresponding calculation cycles and energy consumption data to verify the correctness of the calculation cycles and energy consumption method which we presented.Secondly,we propose a neural network accelerator design scheme based on heterogeneous chiplets,which provides a feasible solution for the interface signal design and interconnection communication mechanism of heterogeneous chiplets.We refer to the obtained neural network accelerator calculation cycle and energy consumption estimation model,and use a coarse-grained load splitting method to guide the design selection of load mapping and chiplets design.The heterogeneous chiplets neural network accelerator designed by this method has a speedup ratio of 3.6 times compared with a homogeneous design,and a speedup ratio of 1.5 times compared to any combination of heterogeneous chiplets.