High-Speed 8KX16 SRAM Circuit Design And Implement Applied To Asynchronous SRAM

With the rapid development of information technology,embedded So C technology is widely used in portable electronic devices,has become an important pillar of the integrated circuit development.Static random access memory(SRAM)is an important part of processor or So C,whose performance such as power,speed,area restrict the development of processor or So C.With the development of the technology process and circuit structure,SRAM performance has been greatly improved,large capacity and high performance designing is still key research of SRAM.Because of 72 M asynchronous SRAM design requirements,The article designed 8KX16 SRAM that based on 65 nm process.In the worst condition of PVT,the pre-layout simulation shows that the working speed of the 8KX16 SRAM is 2.28 ns,under tt condition the speed is 1.47 ns,which meet the design requirement.Finally the layout of 8KX16 SRAM is designed with full-custom design method.This paper mainly focus on the peripheral circuit of decoding circuit,sense amplifier circuits and full custom layout.In order to meet the requirements of high speed and high stability decoder,this paper apply two level static decoder structure.MOS size of the decoder delay chain is designed with logical effort theory to make the speed of decoding fastest.By Hspice simulation,the decoder delay is 0.339 ns in the tt condition.In this paper,a three level amplified sense amplifier circuit is designed based on current mirror type sense amplifier,cross-coupling type sense amplifier as a first stage,a current mirror type sense amplifier for the second stage,the push-pull circuit for the third stage.Under tt conditions,the sense amplifier delay is 0.207 ns by Hspice simulation.The speed is significantly improved compared to single-stage amplifier.Finally,on the 8KX16 SRAM layout design was desicreabed in detail.