Design Of Neural Network Accelerator Based On Hybrid Bus Arbitration Of Data/Device

Convolutional neural network is one of the main technologies of artificial intelligence.Now it has been successfully applied in the following fields:face recognition,image detection and recognition,unmanned driving,medical care,etc.,and has made great contributions to the development of society.However,the contradiction between the computing speed of convolutional neural network and the huge demand for computing resources and memory resources limits its application range.With the advent of the Internet of Things and the era of intelligence,the hardware accelerator design of convolutional neural networks has become a research hotspot in the field of artificial intelligence and digital integrated circuit design.Aiming at the fully connected layer of the convolutional neural network,this article first reduces the storage space occupied by the model parameters and the bandwidth required for calculation through parameter model compression techniques such as pruning and quantization.Then the weighted secondary indexing scheme is proposed.The scheme combines parameter compression to optimize the computing resources of the fully-connected layer,and based on this,the hardware accelerator of the fully-connected layer is designed.The accelerator effectively improves the computing efficiency of the fully connected layer,reduces resource consumption,and makes the calculation of the fully connected layer no longer need to occupy the bandwidth resources of external storage.This allows convolutional layer calculations and fully connected layer calculations to run in a pipelined manner,and improves the overall computational efficiency of the convolutional neural network accelerator.The calculation of convolutional neural network involves a large amount of data and parameters,and the scheduling of signals seriously affects the parallelism of convolutional neural network operations.Due to the different requirements for bandwidth and computing resources of each processing unit and different computing moments of the convolutional neural network,this paper proposes a three-level hybrid bus arbitration protocol based on the amount of data cache and device priority.The hybrid bus arbitration protocol can be used as a general bus protocol for various convolutional neural network accelerator designs.The convolutional neural network accelerator designed with a hybrid bus arbitration protocol can reduce the redundant time of data exchange inside the accelerator,effectively.improve the bandwidth utilization rate inside the convolutional neural network,ensure the parallelism of each processing unit to the greatest extent,and improve the calculation efficiency of the accelerator.Based on the bus protocol of data and device hybrid arbitration,combined with the acceleration strategy of full connection layer and convolutional layer proposed in this paper,the hardware acceleration design of VGG16 and SqueezeNet convolutional neural network is completed.The experimental results show that the proposed acceleration scheme can effectively improve the calculation efficiency and data throughput rate.