Design And Implementation Of A Low Latency DRAM Memory Circuit

Dynamic Random Access Memory(DRAM)has been widely used in various electronic devices due to its low cost and high capacity.Since the invention of DRAM,his capacity and bandwidth have made extraordinary progress,but due to incompatible characteristics with cost,latency has not been well improved,memory latency has become a bottleneck in the performance of computer systems,and optimizing latency is a problem that needs to be solved.This thesis uses the Cadence Virtuoso software to design a 256Kbit DRAM memory using the power chip 25nm process,and uses a structure with an overcharge voltage circuit and a precharge circuit for delay optimization to reduce tRCD and tRP.The work in this thesis has three main components.1、The causes of DRAM generation are explained,three methods of latency optimization are introduced according to the different causes of generation,and a low latency architecture method is selected for latency optimization design.The basic DRAM operations and important timings are then introduced,and the delays between the various operations and the effect of changes in the state of the bit lines on the delays are described.2、Designing the overall structure of the circuity the array of memory cells and the peripheral circuits.Once the individual circuits have been designed,they are integrated and simulated using Finesim software.Simulation results show that the circuit can perform sequential write and sequential read operations correctly.The bitline simulation results are analyzed to verify the presence of tRCD and tRP delays.3、The effect of storage array voltage on latency is analysed.A sensitive amplifier structure with an overdrive voltage circuit and a precharge circuit is used to quickly sense and amplify and pre-charge the bit lines according to the relationship between the storage array voltage and the bit lines.The circuit allows for delay optimisation and the superiority of the structure is verified by simulation comparisons.