Analysis And Research On Metal Interconnection Failure Of Heterogeneous Integrated Modules

Heterogeneous integration integrates different materials and processes to improve the performance of chip.The development of heterogeneous devices is flexible and can achieve better performance and functions when design.More factors are involved in failure analysis,reliability evaluation and test than single chip,which needs further research.This paper studies several failure phenomena of heterogeneous integration,analyzes failure mechanism through reliability test and analysis tools.The first is wafer bonding organic pollution.It is concluded that dielectric layer stripping is an effective sample treatment method.It is difficult to directly observe,test 3D integrated module.It is found that the pretreatment methods such as diamond knife crack and grinding sample preparation can reduce the difficulty of failure analysis.The analysis results show that the organic barrier between metal layers in double-layer wiring and the holes and cracks at the wafer bonding interface due to organic pollution will cause abnormal metal interconnection.Several failure modes and mechanisms of metal interconnection system are recognized.Secondly,the high accelerated life test of a fan-in package chip at 300℃ and 40h is carried out,and it is found that the Au-Al contact interface will have mutual solution failure.The simulation test of Au-TiW-Al plane structure is designed,and it is determined that the failure mechanism is metal diffusion caused by the poor quality of TiW barrier film.In order to find a better diffusion barrier,the simulation tests of Au-Mo-Al and Au-Ni-Pd-Al are designed.The results show that Ni in Au-Ni-Pd-Al structure can block the mutual dissolution of Au and Al,which can be applied to the contact interface of heterogeneous metals in fan in packaging.Finally,the abnormal TSV and back leakage are studied,and morphology of metal layer are analyzed.The reason for the abnormal is metal delamination caused by weak adhesion between Cu and adhesive layer.The reason for back leakage is that when etching the dielectric layer,the warpage of wafer causes offset of dielectric layer,which can not insulate the Si substrate from the Cu column.The research increases cognition of failure mechanism that may correspond to abnormal TSV resistance.