Digital Backend Design For 5G Channel Encode

With the advent of the era of intelligence and informatization,the integrated circuit industry and 5G information technology have ushered in subversive development.At this time,the back-end design of 5G communication chips has become more and more important.With the deepening of research,people have found that The LDPC code can also approach the Shannon limit.This paper successfully designs the digital back-end layout of the 5G channel LDPC code encoder under the28 nm process.The main work is as follows:(1)Use the Design Compiler tool to complete the synthesis of the 5G channel encoder under the 28 nm process.During the synthesis process,set the input/output delay strictly according to the manual and iteratively try the best SDC port constraints;(2)Use the Innovus tool,the synthesized netlist and the library files under the28 nm process to complete the layout and wiring of the 5G channel encoder,and publish the prototype of the drawing;(3)Use Starrc to obtain the Spef file under the 28 nm process and use it in conjunction with the Prime Time tool to generate the SDF timing file to perform static timing analysis on the design,and finally cooperate with the Innovus tool to complete the timing closure and power consumption analysis of the design;(4)In the final stage of the digital back-end design of the 5G channel encoder,use the Calibre tool to complete the physical verification,use the Formality tool to complete the formal verification,use the Prime Time to complete the timing verification and meet the standard of the Sign Off document under 28 nm.This paper studies the design feasibility of the IP-level digital back-end design of the 5G channel encoder under the 28 nm process,and fully verifies the feasibility of the IP-level back-end design of the 5G channel encoder ASIC chip under this process under the sign-off standard.and meet expected effects such as timing closure and manufacturability.