Design And Theoretical Analysis Study Of The Low Jitter Clock

As the wireless communication technology develop rapidly,clock sources are needed to provide clock signals of different frequencies,such as radar,wifi6,5G communication,Beidou navigation and so on.In order to improve the working accuracy and reduce the bit error rate,clock sources should have low jitter performance.At the same time,in order to meet usage requirements of different scenarios,clock sources need to provide clock signals of multiple frequency bands.Therefore,it is of great engineering significance to research low-jitter and wide-band clock sources.In order to meet the integrated application requirements of 5G communication and Beidou navigation,a low-jitter clock source circuit with the function of automatic frequency calibration is designed in this paper to provide low-jitter clocks for subsequent phase shifters and multi-phase frequency output channels.Main research contents of this paper are as follows:1.In order to reduce the output jitter of clock sources,a LC VCO with low power consumption and low noise is designed.The tuning capacitor is divided into the coarse tuning part and the fine tuning part and the output frequency range is divided into several sub-bands so as to reduce the frequency tuning gain(K_VCO)and lower VCO noise.2.In order to lock the frequency locking under small K_VCO conditions,an automatic frequency calibration circuit（AFC）is designed to overcome resonant frequency variations caused by PVT and realize the accurate selection of VCO frequency bands.Pre-selection and sequential search algorithm is applied to AFC circuit,which can overcome the problem of long time caused by traditional sequential search.This greatly reduces the frequency band search time,improves the search accuracy,and realizes the optimal selection of frequency bands.3.In order to reduce the noise in the phase lock ring,a high impedance charge pump structure is proposed in this paper.By increasing the charge pump output impedance,the matching scope can be wider and the matching accuracy can be higher than traditional charge pumps.The voltage matching range is between 0.19 V-0.88 V and the maximum power loss allocation is less than 0.2%.When the input signal phase difference is zero,the average output current is only 2.02 n A.This can help realize better matching performance compared with traditional structures.The low jitter clock was designed in 40 nm CMOS process with the outputting 5.9GHz～6.4 GHz frequency signals.When the supply voltage was 1.1 V,the input reference frequency was 50 MHz,the result show that the clock source bandwidth is 0.83 MHz,the power less than 6.5 m W@6 GHz,the output phase noise is-113.3 d Bc/Hz@1 MHz,the peak-to-peak jitter is 5.84 ps@6 GHz,the rms jitter is 503 fs@6 GHz,reference spur is-62.3 d Bc.