Research On High Efficient Memory And Computing Integration Technology Based On SRAM Structure

The application of AI algorithms has been expanding in recent years,and the demand for energy-efficient AI algorithm hardware implementations in cloud-side applications has been gradually increasing.Currently,AI algorithms mainly use the graphics processing unit(GPU)computing acceleration platform to achieve point multiplication and accumulation computation,however,due to the "von Neumann" architecture mainly used in GPUs,there are "memory walls" and "power walls" bottlenecks,the huge power consumption and speed consumption caused by the frequent movement of data between computing units and memory units,which limits the further development of AI technology,the compute-inmemory(CIM)which implements the computing process directly in the memory subarrays,is expected to break this bottleneck and is considered as a promising architecture.The main research includes:1、An in-memory computing circuit for 8T SRAM applied to Binary convolution Neural Networks(BNN)is designed.By designing the modules of bias voltage,control timing,and analog-to-digital converter coding structure of the core 8*72 memory array,the data storage and dot product accumulation operation are realized by using 8-channel parallel operation,which improves the computational speed and power consumption of in-memory computation dot product summation.The designed circuit utilizes 3-bit ADC eight-bit output coding to complete the dot product summation calculation of 64 bit eigenvalues and weight values,and outputs 8-bit temperature codes with a calculation cycle of 296 ns and an energy efficiency of the 1 bit operation is 1.69 GOPS/W with a maximum average calculation deviation of 1.05%.2、A multi-phase sampling in-memory computation circuit is proposed and a weighted adaptive symbolic judgment circuit is also added,which can balance the number of bitline discharge cells,improve the discharge linearity,and achieve summation computation comparison output at different phases of one clock cycle to improve the computation accuracy.Simulations show that using a core supply voltage of 0.8 V/1.2 V and a clock frequency of 250 MHz,a maximum 64 bit thermometer code comparison output is achieved with a computation cycle of 560 ns and an energy efficiency of the 1 bit operation is 1.67GOPS/W with a maximum average computation deviation of 0.67%.Based on the standard CMOS 65 nm process,this thesis implements the design of the in-memory computing timing control module,core array and layout.The simulation shows that the solution can solve the memory wall problem of data storage,transportation and computation with high performance,high speed and high accuracy,which is of great significance in the field of artificial intelligence to promote the development of analog circuits for the implementation of in-memory computing technology.