Design Of All Digital Phase Lock Loop For SoC Clock Generation

The development of integrated circuits technology,the all digital phase-locked loop(ADPLL)have better integration,easier portability,lower cost and lower sensitivity to noise.Now,highly digital clock generator architecture,most commonly implemented using all digital phase-locked loops,is evolving as the preferred means for System on Chip(SoC).They are widely employed in various applications such as cellular phones,wireless products,personal computers,laptops,televisions,and wireless transceivers.Based on the application of the system-on-chip clock generator,this dissertation focuses on the research and design of an all digital phase-locked loop with low power consumption,small area and wide frequency tuning range.The works of the dissertation are listed in the following:1)According to the background of the clock generator applied to SoC,the structure of the all digital phase-locked loop with frequency accumulation type is determined,the performance index of the all-digital phase-locked loop is deduced,and the stability of system is verified based on Matlab,the sub-module circuits of the all digital phase-locked loop are modeled by Verilog language,and the effectiveness of the architecture is verified by cadence simulation platform.2)A time-to-digital converter(TDC)structure based on ring oscillator(RO)is proposed.The delay chain of the TDC is composed of a gated multi-phase ring oscillator and a counter.Combined with the phase detection circuit designed in this paper,the quantization error caused by the instability of the cycle can be reduced when the oscillator is started.Compared with the traditional TDC based on delay chain,the proposed TDC circuit achieves a better compromise between phase detection accuracy and dynamic range and occupies a lesser area.3)A gain-adjustable digitally controlled oscillator(DCO)is proposed.Firstly,the DCO uses a high linearity digital-to-analog converter(DAC)to achieve good jitter performance and frequency accuracy,and it contains a three-level current source array;secondly,it uses a modulator to modulate the fine-level current source array control word in order to improve the frequency resolution;in addition,this digitally controlled oscillator uses the dynamic element matching method to switch the fine-level current source array and improve the linearity of the DCO tuning.4)A circuit is designed to detect the locked state of the phase-locked loop by judging the instantaneous value of the phase error.The clock generator for the SoC system is designed and fabricated in the TSMC 40nm CMOS process,and the chip area only occupies 0.1mm~2.The simulation results show that the output frequency tuning range of the phase-locked loop is 500～1500 MHz under the 1.1V supply voltage,the phase noise is-90～-92 dBc/Hz at 1MHz frequency offset,and the RMS jitter is less than 15 ps.