Phase Synchronization Design Of Multi-chip Fractional Phase Locked Loop

With the rapid development of wireless communication technology,the requirements for the clock are getting higher and higher.Clock jitter and clock phase consistency have a great impact on system performance,Multiple Input Multiple Output(MIMO)technology is one of the most effective ways to improve the transmission reliability and data rate of the system.Since the fractional phase-locked loop can provide a flexible clock signal,it is often used to generate the local oscillator signal in MIMO systems.In a massive MIMO system,multiple fractional phase-locked loops are required,and a common reference clock signal is used to generate a local oscillator signal with the same phase signal.Different from the integer phase-locked loop,the output phase of the fractional phase-locked loop has uncertainty under the influence of PVT.In order to solve this uncertainty,this thesis conducts in-depth research on the PLL phase synchronization.First,based on the Simulink model of the fractional phase-locked loop,the loop parameters are calculated,and the fractional phase-locked loop with temperature compensation VCO is designed.In the temperature compensation VCO,a calibration circuit and a bias circuit are designed,the output voltage changes with the temperature,and then the capacitance of the variable capacitor is tuned to adjust the VCO output frequency.To synchronize the fractional phase-locked loop output,a phase synchronization algorithm is designed.In the phase synchronization module,the phase reference of multiple fractional phase-locked loops is adjusted according to the synchronization signal MCS.The output of the VCO is sampled and compared with the tracking signal to obtain the phase difference,and a feedback signal is generated to adjust the fractional fraction of the fractional phase-locked loopΔΣ modulator.frequency ratio,thereby adjusting the phase of the phase-locked loop output signal.The results are realized: the phase synchronization algorithm and the fractional phase-locked loop simulation model are jointly debugged by AMS.When the input frequency is 20 MHz and the frequency division ratio is 10.1,the output phase synchronization of multiple fractional phase-locked loops is realized,and the phase adjustment time is 4ms.This article is based on TSMC 65 nm CMOS process tape out a fractional phase-locked loop with temperature compensated VCO,and conducts phase noise and jitter performance tests.The reference signal frequency is 80 MHz,and the RMS jitter values are 0.3508 ps,0.3364 ps,and 0.0716 ps at three frequency points of low frequency 625 MHz,intermediate frequency 2.5GHz,and high frequency 5.2GHz,respectively.