Design And Implementation Of Hardware-in-the-loop Simulation For Small Data Packet Transmission Technology Based On 5G Random Access

In the current mobile communication network,air interface resources are still the most scarce resource.At the same time,in the environment of the surge in the number of intelligent terminals,the variety of data services,and the growing proportion of small data packet services,the future 5G communication system needs Supports efficient small data transmission seamlessly with current cellular networks and fast and flexible switching between different wireless transmission technologies.This kind of small data packet service has two obvious characteristics.One is that the total traffic of small data packets is very small,but each time the accompanying signaling accounts for a large proportion,which brings a lot of waste of resources to the system;the other is that this service Users are required to be always online and have a heartbeat phenomenon,resulting in a huge number of online users in the network,and a time delay will be introduced when multiple users access.In order to solve the problem of small data transmission efficiency in 5G and B5G systems,the enhancement technology of small data transmission based on random access in the inactive state has been widely studied.Therefore,it is of great significance to study the small data transmission enhancement technology in the 5G communication system to alleviate the waste of resources and reduce the delay.The topic of this paper comes from the key research and development plan of the Ministry of Science and Technology "Construction of B5G and 6G Public Service Platforms".Based on the development of the air interface(OpenAirInterface,OAI),a hardware-in-the-loop simulation platform suitable for small and medium data transmission enhancement in 5G communication systems is designed and implemented.Based on this platform,the simulation verification and performance analysis of the small data transmission enhancement technology of 5G communication system are carried out,which provides a theoretical reference for standardization work.The main work of this paper is as follows:Firstly,design of hardware-in-the-loop simulation platform for small data transmission technology based on 5G random access.In this paper,the requirement analysis and overall design are firstly carried out,and according to the functional requirements of the small data transmission enhancement technology based on random access in the 5G communication system,the small data packet transmission enhancement based on four-step random access is designed first.The design is based on the enhancement of small data transmission of two-step random access,focusing on the design of the physical layer function module,the MAC layer function module and the PHY/MAC layer interface module,so that the two network elements of the base station and the terminal in the hardware-in-the-loop platform can achieve high efficiency small data transfer enhancements.Secondly,implementation and verification of the hardware-in-theloop simulation platform based on 5G random access enhancement technology for small data transmission.First,under the guidance of the module design idea,the development and realization of the enhanced hardware-in-the-loop simulation of small data transmission based on fourstep and two-step random access is completed.The realization process involves multiple protocol layers and multiple channels of network elements on the base station and terminal side.And the interface exchanged between layers.Secondly,the functional verification and performance evaluation of the hardware-in-the-loop simulation platform are carried out from the signaling and data planes.The simulation results show that the platform can complete the enhanced communication simulation of small data transmission based on 5G random access on the basis of being backward compatible with the functions of the original platform,and has significantly improved the transmission delay and signaling overhead of small data packets.The feasibility of the hardware-in-the-loop simulation platform designed in this paper is proved,and the development results of this paper provide a test and experimental platform for the follow-up research and development of the project.