Design And Implementation Of Low-complexity LDBCH Decoding Algorithm

This paper mainly studies a low-density BCH-constraint(LDBCH)codes,analyzes LDBCH code encoding and decoding algorithm,and designs the encoder and decoder of LDBCH codes.For the application of Ultra Reliable Low Latency Communication(URLLC)in 5G,the coding and decoding algorithms of LDPC codes at very Low bit rates are very complicated.The LDBCH codes composed of Generalized LDPC(GLDPC)component codes using BCH codes is an efficient low-rate coding method,which can effectively improve the transmission performance in noisy channels.However,LDBCH codes has some problems such as high decoding complexity and hard hardware implementation,which restrict its practical engineering application.Based on decoding algorithm and hardware design,this paper aims to reduce the complexity of decoding algorithm without losing decoding performance as much as possible,and realize the hardware design with lower complexity.First of all,aiming at the problem that the decoding complexity and decoding performance of LDBCH codes are difficult to balance,this paper uses max-log-map algorithm to approximate the decoding performance,and makes a reasonable compromise between the decoding performance and implementation complexity,reducing the complexity of the decoding algorithm without losing the decoding performance as much as possible.Secondly,in the design of encoder LDBCH codes,analyses the composition of LDBCH code words,at the top of the encoder design is given,and the son of the encoder module and internal function of the structure of the input and output analysis,this paper discusses the code word memory and the way of addressing the design and the corresponding degree of different BCH coding input control,and(7,4)BCH coding module is taken as an example to demonstrate the hardware design of BCH coding processing unit.Finally,in the design of LDBCH decoder,the decoding design of BCH check node adopts soft-in soft-out(SISO)decoding algorithm with maximum posterior probability.Although its decoding performance is good,the standard SISO algorithm is complex and difficult to implement.Therefore,for the decoding algorithm of THE BCH check node,this paper uses the butterfly structure to reduce the computation of the BCH soft decoding,and uses the minimum sum algorithm for the single parity check bits to further reduce the computation of the hardware implementation.This combined decoding method greatly reduces the computation of the hardware implementation of the LDBCH code decoding.In the design of LDBCH code decoder,the connection relation between the top module and the sub-module of the decoder is shown with the specific design diagram,and the coming and going trend of the code word bit stream in the decoder is explained in detail.The hardware realization algorithm at the BCH decoding node is explained in detail with the(7,4)BCH decoding sub-module as an example.