FPGA Design And Experimental Verification Of Polarization Multiplexing Module In High Speed Spatial PM-QPSK Coherent Optical Communication Receiver

With the rapid development of Internet technology,real-time communication services such as platform live broadcasting and "face to face" cloud conference based on real-time communication are also developing rapidly.Traditional communication networks are facing increasing pressure of communication bandwidth.Compared with traditional microwave communication,satellite-ground laser communication system has smaller terminal volume,lower power consumption and higher transmission speed,which is the development direction of the next generation communication system to solve the transmission bottleneck of traditional microwave communication system.In the actual transmission process,the satellite-ground laser communication will be affected by the atmospheric channel,resulting in a certain degree of distortion of the laser signal.At present,there are few Digital Signal Processing(DSP)algorithms for space channel compensation,so the design and implementation can meet the transmission rate requirements of space optical communication system and the low complexity real-time parallel DSP algorithm suitable for the system has become the hot spot and difficult point of current research.This paper mainly focuses on the design of polarization demultiplexing algorithm in optical receiver of 1.25GBaud PM-QPSK high-speed spatial coherent communication system and its hardware implementation based on Field Programmable Gate Array(FPGA).The main research contents are as follows:(1)Based on the design requirements of low power consumption of hardware resources,an improved parallel polarization demultiplexing algorithm with low complexity suitable for FPGA hardware implementation is studied and designed.In this paper,serial and parallel polarization demultiplexing algorithms based on constant mode algorithm are studied.Aiming at the problem of high resource consumption and poor convergence effect of parallel demultiplexing algorithm,the error calculation scheme of parallel algorithm has been improved.Simulation results show that compared with the traditional parallel algorithm,the convergence accuracy of the improved parallel polarization demultiplexing algorithm is improved by about 50%,and the number of addition and multiplication is reduced by about 45%,which is suitable for large-scale parallel FPGA implementation.(2)Based on Altera’s 5SGXMA7K2F40C3 FPGA chip,an improved parallel polarization demultiplexing algorithm for 1.25gbaud rate PM-QPSK spatial coherent optical communication system is designed and implemented.In the realization,a pipeline is adopted to update tap coefficients successively,which can satisfy the system throughput with lower resource occupation at the cost of a certain convergence speed.Function simulation results show that the Verilog code functions are consistent with simulation platform.The compilation results show that compared with the traditional parallel algorithm,the FPGA hardware resource consumption of the improved parallel polarization demultiplexing algorithm is reduced to 30%,which greatly reduces the hardware resource consumption.(3)The online real-time experimental verification of the improved parallel polarization demultiplexing algorithm under the indoor FSO analog channel is completed.The experimental results show that when the sensitivity of the system receiver using the improved algorithm is greater than-33dBm,the system bit error rate is less than 7 × 10-5.