Research On Wafer Defect Detection And Drying Technology Based On Function Recombination And Its Integrated Device

In recent years,with the increasing demand for chips in the market,domestic and foreign semiconductor manufacturers reduce production costs by increasing the yield of semiconductor products,so as to improve production capacity.In the process of semiconductor manufacturing,the most important material is wafer,and the yield of wafer has a great impact on the whole semiconductor industry chain.In the wafer production process,a complex process is needed.After a series of major processes such as photolithography and etching,cleaning,drying and testing are carried out.These processes are collectively referred to as post-treatment processes in this paper.The three post-treatment processes of wafer cleaning,drying and testing run through the entire manufacturing process of wafers.The front cleaning process of wafers is mainly to remove the particles falling on the surface of wafers to ensure the cleanliness of the surface.After that,drying process is carried out to remove the water on the surface of wafers.Reduce the yield of the wafer.Inspection steps almost always exist in the processing process,because the quality of the wafer needs to be guaranteed before the next process,timely selection of products with defects to prevent them from entering the next process,otherwise it will increase the manufacturing cost of the semiconductor.The main research content of this paper is wafer surface defect detection technology and wafer full drying technology and integrated device.Firstly,the patterned wafer surface has complex circuit background and large defect scale changes,and the traditional visual detection algorithm will lead to false detection and missing of defects.Therefore,a new wafer surface defect detection algorithm based on double attention fine up-sampling is proposed.The algorithm uses Faster R-CNN network as the framework and ResNet50 as the backbone for network extraction.Firstly,two different attention modules are embedded to extract more edge information in the low-level Feature stage.Therefore,before input into the FPN(Feature pyramid networks)network,the extracted features are optimized through the channel attention model.In the high-level feature stage,more attention is paid to the semantic information of the image.Therefore,the extracted features are optimized through the spatial attention model to highlight the semantic information of the focus area,so as to enhance the network’s attention to the target defects and further emphasize the importance of the target defects.Secondly,in order to improve the accuracy of small target defect detection,the up-sampling part of the original FPN is improved,and Fine up-samplin g is proposed.Bilinear interpolation is carried out on the features after mask,aiming at reducing the loss of feature information in the up-sampling process,so as to obtain more accurate feature information.The test results show that the mAP of the proposed method in wafer surface defect detection task reaches 97.31%,which is 11.33%higher than that of Faster RCNN+CBAM,and satisfactory results can still be obtained under the background of complex circuits.Secondly,to solve the problems in wafer drying process based on Marangoni effect,such as low film formation rate due to the imbalance of IPA gas atmosphere in the tank,a bipolar buffer gasification dispersion mechanism was designed to form a balanced area on the surface of pure water and improve the film formation efficiency.Due to the static state of the wafer during drying,the contact area between the wafer and the wafer boat has the problem of insufficient drying and residual water marks.Therefore,a full drying mechanism based on the Z-shaped micro-wavering pendulum wafer surface is proposed to make a transient gap exist between the wafer and the wafer boat to achieve full drying.Finally,based on the above two kinds of post-processing technology research,the modular design,the development of wafer post-processing technology integration device,design of automatic handling mechanism,avoid manual participation,improve the degree of automation.Experimental verification:compared with the traditional independent postprocessing technology,the integrated device processing technology,its floor area is only 1.95mm~2,compared with the traditional post-processing device to save 15% of the floor area.