| With the development of wireless communication technology,Class-E power amplifiers(PAs)are widely used in various radio frequency(RF)transmitters.Its research is developing towards high efficiency,low power consumption and high integration.PAs have important practical significance for the development of wireless communication technology.In this thesis,two Class-E PA chips used in 433 MHz wireless voice communication are presented.For this target application,they have advantages of high efficiency,small area and low power consumption,etc.Firstly,this thesis expounded on the development process of PAs,followed by a literature review.Secondly,it introduced specifications for PAs,BPSK mixing technology and impedance matching technology used in PAs.And it provided a detailed explanation of operating principle and characteristics of all kinds of PAs.Thirdly,the design methods for Class-E PA with finite DC-feed inductance and infinite DC-feed inductance were presented.Especially it derived the design equations of PAs’ load network in detail.Designing and improving the load network was the main foucus and challenge of this thesis’s research.Finally,two 433 MHz Class-E PA chips based on passive mixing topology and active mixing topology were respectively designed for different requirements of carrier signal source,linearity and power gain.The difference between this two chips lies in the mixer circuit and driver circuit.In addition,this thesis presented the design of the gain controlled power stage circuit for low power consumption requirements.PA has four operating modes for different output power,and its output power is-6 dBm,-3 dBm,0 dBm and 3 dBm respectively.In this thesis,the schematic and layout of 433 MHz Class-E PA were designed using UMC 55 nm CMOS process.And pre-layout simulation,post-layout simulation,chip fabrication and testing were finished.Under the conditions that the operating voltage of driver stage is 1.2 V,the operating voltage of power stage 1.8 V,process corner is TT and temperature is 27℃,results of post-layout simulation are as follows:for Class-E PA with active mixing topology,when input signal is 200 mVpp@433 MHz,output power is 3.8 dBm@433 MHz,power-added efficiency is 40%,total power consumption is 5.87 mW,and the error vector magnitude(EVM)is about 2.08%rms;for Class-E PA with passive mixing topology,when input signal is 400 mVpp@433 MHz,output power is 3.7 dBm@433 MHz,power-added efficiency is 40.3%,total power consumption is 5.34 mW,and the EVM is about 2.20%rms.Both PA chips can switch four operating modes accurately.Actual measured results of these two chips are as follows:S22<-10 dB within the frequency band from 393.79 MHz to 455.70 MHz;for Class-E PA with active mixing topology,when input signal is 200 mVpp@433 MHz,its output power is 2.95 dBm@433 MHz,the EVM is about 0.83%rms with 192 kbps BPSK data modulated at 433 MHz,total power consumption is 6.72 mW,and the chip area is 0.287 mm2;for Class-E PA with passive mixing topology,when input signal is 400 mVpp@433MHz,its output power is 2.61 dBm@433.07 MHz,the EVM is about 1.64%rms with 192 kbps BPSK data modulated at 433 MHz,total power consumption is 6.66 mW,and the chip area is 0.287 mm2. |
