Research On Area Optimization And Power Optimization Approaches For Multi-output Mixed-polarity Reed-Muller Logic Circuits

Integrated circuits significant role in artificial intelligence,aerospace,medicine and computer manufacturing,and are the cornerstone of the information age.In order to solve the design problems of complex integrated circuits,Electronic Design Automation (EDA)technology was created.EDA uses Computer Aided Design (CAD) technology to complete the design of complex integrated circuits.EDA synthesis tools can generate and optimize target circuits,and circuit optimization is an important part of logic synthesis.The Boolean logic based on"AND/OR/NOT" and the Reed-Muller (RM) logic based on"AND/XOR" are two important expressions of digital logic.Numerous researches have shown that RM logic circuits are better than Boolean logic circuits in terms of area,power,and testability on some circuits.Current research on RM logic circuits has focused on single output circuits, with less research related to multi-output RM logic circuits.In addition,multi-output RM logic circuits require more output variables to be considered and polarity conversion algorithms are more cumbersome than the conversion algorithms for single-output RM logic circuits.This paper addresses the problems of inefficient polarity conversion approaches from Boolean logic circuits to RM logic circuits and the inefficient polarity conversion approaches between different RM logic circuits,and poor area optimisation and power optimisation of multi-output MPRM logic circuits.The main work of this paper is described as follows.(1) A circuit conversion algorithm of Boolean logic circuit to RM logic circuit based on two binary treesThis paper proposes a polarity conversion algorithm from Boolean logic circuits to RM logic circuits based on two binary trees (BRPTBT) to address the problem of low conversion efficiency of polarity conversion algorithms from Boolean logic circuits to RM logic circuits.BRPTBT dynamically deletes,adds,finds,and removes duplicate minima on the binary tree A-Ⅰ according to the corresponding polarity bit values,and then stores the minimum items that are valid on the A-Ⅰ tree in the A-Ⅱ tree.Thus,achieving a fast polarity conversion from Boolean logic circuits to RM logic circuits.Experimental results based on the Microelectronics Center of North Carolina (MCNC) benchmark test circuit show that the conversion efficiency of BRPTBT is improved by up to 99.97% compared with mixed polarity conversion algorithm based on list technique (MPCLT).(2) A polarity conversion algorithm between different RM logic circuits based on two binary treesThis paper proposes a polarity conversion algorithm between different RM logic circuits based on two binary trees (PDRTBT) to address the problem of low conversion efficiency of polarity conversion algorithms between different RM logic circuits.PDRTBT dynamically deletes,adds,finds and removes duplicate minima on the binary tree A-Ⅰ according to the corresponding polarity bit values,and then stores the minimum items valid on the A-Ⅰ tree in the A-Ⅱ tree,thus achieving a fast polarity conversion between different RM logic circuits.Experimental results based on the MCNC benchmark test circuit show that the conversion efficiency of PDRTBT is improved by up to 99.47% compared with mixed polarity interconversion algorithm based on list technique (MPILT).(3) An area optimization approach for multi-output MPRM logic circuits based on a whale optimization algorithm with an explosion and restart strategiesTo address the problem of poor area optimization of multi-output MPRM logic circuits,this paper proposes a restart and explosion strategy based whale optimization algorithm(REWOA),and then proposes a multi-output MPRM logic circuit area optimization approach based on REWOA(AOPMM).The approach introduces a restart strategy based on the standard whale optimization algorithm (WOA),which enriches the diversity of the population and increases the probability of the algorithm jumping out of the local optimal solution.The introduction of the explosion strategy increases the search range of the population and speeds up the convergence speed of WOA.The experimental results based on the MCNC benchmark test circuit show that the average circuit area saving of AOPMM is 3.77% and the maximum circuit area saving is 9.72% compared with WOA;the average circuit area saving of the improved WOA is 5.54% and the maximum circuit area saving is 18.32% compared with the genetic algorithm;the average circuit area saving of the improved WOA is 5.00% and the maximum circuit area saving is 14.41% compared with the artificial bee colony algorithm.(4) A power optimization approach for multi-output MPRM logic circuits based on two-population and mutation strategies for WOATo address the problem of poor power optimization of multi-output MPRM logic circuits,this paper proposes a two-population and mutation strategy based whale optimization algorithm (TMWOA),and then proposes a multi-output MPRM logic circuit power optimization approach based on TMWOA(POAMM).The approach is based on the standard WOA,and by introducing a two-population strategy,the algorithm has two ways to update the position of individuals in the iterative process,which further increases the diversity of the population and improves the convergence ability of the algorithm;it increases the local search ability of the algorithm by introducing a mutation strategy,which enhances the ability of the algorithm to jump out of the local optimal solution.Experimental results based on the MCNC benchmark test circuit show an average circuit power savings of 8.94% and a maximum circuit power savings of 31.47% compared with the genetic algorithm.Compared with the genetic algorithm-discrete triple-valued particle swarm optimization (GA-DTPSO),the average circuit power saving is 1.77% and the maximum circuit power saving is 11.10%.Compared with the Discrete Whale Optimization algorithm (DWOA),the average circuit power savings is 5.39% and the maximum circuit power savings is 21.85%.