Validation Of The CPU Cores Based On The RISC-V Architecture

The integration and complexity of integrated circuits have significantly increased,and the completeness and correctness of complex and massive IP functions are difficult to guarantee.As an important aspect of ensuring chip design quality,verification work requires a lot of cost and effort,and gradually becomes a key link in chip design.In recent years,RISC-V processors have developed rapidly.As a new reduced instruction set,RISC-V verification work faces problems such as limited test sets,imprecise reference models,and chaotic verification methods.Therefore,this article builds a UVM verification platform based on the RISC-V architecture CPU core independently designed by the team,and conducts verification of CPU core timing and functionality.Firstly,the RISC-V instruction set architecture,instruction format and floating point representation are analyzed,the pipeline technology of CPU core is studied,the technical characteristics of UVM verification methodology are analyzed,and the overall architecture and verification scheme of UVM verification platform are planned from the aspects of structural components,target tasks and reusability.Secondly,a thorough study was conducted on the hierarchical structure,operational process,and communication mechanism of the UVM verification platform.The core components of the UVM verification platform,including transaction base classes,Sequences,Sequencers,driver modules,monitoring modules,environment components,reference models,and scoreboards,were designed in detail.Then,the function and structure of floating-point operation unit in CPU core are analyzed in detail,including floating-point addition unit,floating-point multiplication and division unit,floating-point register stack,and floating point addition,subtraction,multiplication and division algorithms;Focused on the overall design and detailed design of the floating-point operation unit,extracted the Functional verification points,built a UVM verification platform,and completed the Functional verification and simulation results analysis of the floating-point operation unit by generating a large number of complex customizable random excitation,and randomly verifying each running instruction.Finally,taking the elevator running controller and AHB bus SRAM controller as the objects to be tested,the reusability of the UVM verification platform is deeply explored.The functions and structures of the two objects to be tested are planned,all modules of the two objects to be tested are designed,and the Functional verification points of the two objects to be tested are extracted.Based on the structure and components of the universal UVM verification platform,and combined with the functional characteristics and verification requirements of the two objects to be tested,personalized UVM verification platforms are built respectively.Through the analysis of simulation reports and coverage reports,the high reusability and portability of the UVM platform are proved.