Research On Key Technologies In Integrated Circuit Test Vector Conversion

With the rapid development of integrated circuit(IC)technology,the scale and structural complexity of ICs have been increasing.To ensure the accuracy and completeness of test vectors in IC testing,test vectors are typically generated using electronic design automation(EDA)simulation and verification tools,in formats such as VCD,EVCD,WGL,and STIL.However,due to the fact that the V93000 tester can only recognize binary vectors,vector conversion technology is essential in IC testing to convert simulation vectors to binary vectors.The IC tester is a key device in IC testing that can greatly improve testing efficiency.However,the international situation has affected the stable supply of IC testers by foreign companies due to the chip bill proposed by the US government,which has restricted the development of China’s semiconductor industry.Therefore,the localization of IC automatic testers and vector conversion systems is of great significance for ensuring the stable development of China’s IC industry.This article is based on a project in the laboratory’s IC test vector conversion system,which focuses on the research of vector conversion,timing optimization,vector compilation,and vector compression technologies in the test vector conversion system.The article designs and implements a highly integrated and cross-platform IC test vector conversion system with the following main features:(1)Implementing a highly integrated and platform-compatible test vector conversion system:This system solves the problem of test vectors generated by EDA simulation and verification tools that cannot be recognized by the tester.To address this,the article proposes a step-bystep conversion method using the STIL vector as an interface,including methods for converting VCD,EVCD,and WGL vectors to STIL vectors and for converting STIL vectors to timing and vector files.The system generates a global configuration file and channel file configuration,and utilizes the V93000’s ASCII interface to generate binary timing and vector files.In addition,to address the issue of vector waveform display not supported by existing vector conversion systems,the article proposes a vector parsing and waveform display method that is applicable to various vector types.To enhance platform compatibility,the article uses the Qt framework to implement the client,enabling the system to run on multiple platforms.(2)Proposing a timing optimization method that balances timing accuracy and testing efficiency:To address the issue of the number of transition edges within a single period of a test vector exceeding the upper limit provided by the tester,the article proposes two timing optimization algorithms.The first algorithm controls the maximum number of transition edges within a single period of the converted STIL vector by controlling the division period during VCD-to-STIL conversion using a sliding window.The second algorithm controls the maximum number of transition edges within a single period of the STIL vector by segmenting and merging the timing sequence.(3)Proposing a compression method based on repeated substitution:To address the problem of the small storage depth of the tester and the high cost of increasing storage depth,the article proposes a compression method based on repeated substitution.The method uses LZSS and Huffman coding to perform secondary compression on binary vectors,reducing the storage depth required for storing vectors.The article’s vector compression method is compared and evaluated,and shows a compression efficiency 7.17%higher than differential compression and 28.6%higher than run-length encoding.