The Research On LDPC Encoder And Decoder Of CCSDS Standard

Low Density Parity Check Code(LDPC)is a kind of linear block code.Due to its sparse check matrix and its error correction performance close to Shannon limit,it is widely used in various situations.LDPC codes have excellent encoding and decoding performance.However,improper design often leads to high encoding and decoding complexity in actual use,which consumes too much hardware resources.Therefore,how to achieve as high a throughput rate as possible while using less hardware resources is a problem that needs to be considered.This paper addresses the(8176,7154)LDPC code for near-Earth Space communication in the Consultative Committee for Space Data Systems(CCSDS)standard,A parallel encoder based on quasi-cyclic structure and a partial parallel decoder based on normalized minimum sum algorithm are designed respectively.Firstly,this paper analyzes the basic theoretical knowledge of LDPC code,studies the structural characteristics of LDPC check matrix under CCSDS standard,and focuses on deducing the encoding and decoding principle of LDPC code.The performance of LDPC codes with different encoding and decoding schemes is also discussed.Through theoretical analysis and software simulation,the performance of the decoding algorithm under different conditions is analyzed and compared,and the related parameters such as the final decoding algorithm,iteration times and normalization factor are determined.Finally,the fixed-point quantization scheme of the decoder is studied.Secondly,this paper designs and implements high speed coding for CCSDS standard(8176,7154)LDPC code.After analyzing different coding algorithms,an Accumulator based on quasi-cyclic structure is selected with the lowest coding complexity.Starting with the coding calculation method,Shift Register Adder Accumulator(SRAA)is adopted to complete the design of the overall structure of the encoder in parallel.The final analysis shows that the maximum working frequency of the encoder is 223.31 Mhz,and when the working clock of the encoder is 200 MHz,the encoding throughput can reach 2.8Gbps.Finally,based on the previous research on decoding algorithms,a partial parallel structure decoding scheme is designed and implemented by using the normalized minimum sum decoding algorithm with a normalization factor of 0.75.In order to solve the problem that the information processing delay of check nodes is too large in the decoding process,an improved comparator structure is proposed,which increases the speed of information processing and improves the updating process of check nodes by means of multi-hierarchy association,and reduces the time required for single iteration without increasing the complexity of operation.In this paper,Zynq7100 series device as the research platform,aiming at CCSDS standard(8176,7154)LDPC code,Quasi-Cyslic LDPC,QC-LDPC)decoder is simulated and realized.The results show that the maximum working frequency supported by this decoder can reach100.57 MHz,and when the working clock is 100 MHz and the number of iterations is 10,the resource consumption of the decoder side is 7.82%,and the throughput rate can reach 80 Mbps.This design has practical engineering significance and provides some reference value for other research.