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Design And Implementation Of A Performance C Coroutine Under Smp

Posted on:2024-01-10Degree:MasterType:Thesis
Country:ChinaCandidate:W WangFull Text:PDF
GTID:2568306944957969Subject:Software engineering
Abstract/Summary:PDF Full Text Request
The coroutine model has a wide range of applications in the field of highly concurrent and parallel computing due to its asynchronous and lightweight.With the development of edge computing,the volume and complexity of data generated by sensors have increased dramatically compared with the past,and traditional uniprocessor cannot process these data fast enough,so symmetric multiprocessors(SMP)are widely used because of their excellent performance and modest price.However,the software ecology of symmetric multiprocessors is slow to develop,especially the compatibility with customized hardware and software is uneven.Therefore,it is necessary to design and implement a coroutine model that supports symmetric multiprocessors and is widely compatible with various customized hardware and software for the edge computing ecosystem,which has the asynchronous and lightweight features to process the large amount of data generated by multiple sensors asynchronously faster with symmetric multiprocessors.By studying the coroutine,Libuv,the mainstream multiprocessor scheduling model and processes under Linux.This thesis designs and implements a coroutine model ctask capable of supporting symmetric multiprocessors.In order to make the coroutine model compatible with uniprocessor devices,this paper proposes a compatibility layer for uniprocessors and symmetric multiprocessors.For the characteristics of the coroutine,this paper proposes a symmetric multiprocessor scheduler suitable for the coroutine to take full advantage of the advantages brought by the symmetric multiprocessor.This paper also designs and implements a state management mechanism for the coroutine to ensure that the coroutine does not enter an illegal state,and makes the coroutine model widely compatible with various major instruction set architectures(ISA)and compilation tool chains,including x86-64,AArch32,AArch64,and RISC-V In addition,this paper also provides some optimization of the coroutine model according to the cache and hyperthreading features of symmetric processors.In the testing session,the coroutine model is deployed to the real environment and functional and non-functional tests are conducted.Each module passed the functional test.In the non-functional tests,for the compatibility test,the coroutine model can support 4 ISAs.Regarding performance testing,this paper implements an MQTT Benchmark based on the coroutine model ctask,and after benchmark testing,its average message throughput is 1428.10Mbps,which is only 5.01%different from the commercial product EmqttBench,which meeting the expected level.As shown above,this paper designs and implements a coroutine model with good compatibility and performance,and has positive significance in enriching the software ecology of edge computing.
Keywords/Search Tags:Coroutine, SMP, RISC-V, MQTT
PDF Full Text Request
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