With the rapid development of China’s aerospace technology,the research on the infrared focal array detection in space has attracted more and more attention from researchers.In order to detect,capture and track targets more accurately and quickly,the infrared focal array detection system in space used to transmit high-definition infrared thermal radiation images puts forward extremely high requirements for the transmission rate,reliability and high-definition display of infrared images.Many of image transceiver interfaces are unable to meet the high-definition display requirements for the infrared focal array detection system in space,because their shortcomings such as slow transmission speed,low transmission efficiency,complex wiring and poor of resistance to single particle radiation.Therefore,this article focuses on the above engineering issues,and designs and develops a high-speed and high-definition display transceiver interface that is resistant to single particle irradiation,in order to to meet the application requirements of the infrared detection in space.An equivalent single particle irradiation model which the particle irradiation interference is equivalent to channel noise interference is established to approximate the impact of particle irradiation on the transceiver interface.First of all,aiming at the problem of the traditional architecture can not resist particle radiation,it is proposed to introduce RS error correction code in the physical coding sublayer(PCS).So as to effectively improve the coding gain.Secondly,aiming at the problem of low transmission efficiency and unachievable clock data recovery(CDR)and high coding gain at the same time,a cyclic cascade architecture is proposed to encode the check code with 8B10B again.So that the function of interface is normal,and it can effectively further improve the coding gain.Thirdly,due to the slow speed of traditional interfaces and the tight timing and drive capacity limitations of the high-speed parallel-to-serial conversion circuit,a new scheme for parallel8B/10B coding is proposed and a hierarchical high-speed parallel-to-serial conversion circuit is designed,so as to effectively improve the sending and receiving rate and driving ability.Finally,in the process of hardware circuit implementation,some of mechanisms such as multiple clock domains,pipelines,and gated clocks are introduced to optimize speed and power consumption.Interface design are based on verilog HDL language.And completed the verification of resistance to particle radiation for transceiver interface based on FPGA.Secondly,synthesis,formal verification and placement and routing are performed under the SMIC 0.188)CMOS process.Finally,post-simulation verification is completed through the obtained physical layout.The overall verification results show that the bit error rate of the transceiver interface is as low as 10-10,the number of resistance to particle radiation under the equivalent verification of single particle irradiation is about 107/cm2,the coding gain is increased by about+5 d B,the transmission efficiency is as high as 93.72%,the single channel transmission rate is up to 1 Gbps,and the system power consumption is as low as 63 m W,the layout size is about 0.81 mm2.Therefore,the design can meet the requirements of high-speed and high-definition for the space infrared detection in the low-medium orbit of the earth,and achieve the expected design goal. |