Design Of Multi-phase Delay Locked Loop Applied To High Speed SerDes

Currently,high-speed and unditorted signal transmission between chips is mainly implemented through the serial interface technology.Ser Des is the core component of the serial interface.This thesis focus on the design of MDLL used for Ser Des.With the TSMC 40 nm CMOS standard process,the design of a high accuracy,high speed and 4-phases-output DLL is carried out.The main content of the thesis is presented as the following four parts:(1)In order to overcome the phase error caused by mismatch of delay cells in traditional MDLL implementation under advanced technology,two independent phase detection-control negative feedback loops are proposed to make the phase accuracy of 90° and 270° signals generated through two delay lines unaffected by mismatch.The Verilog-A behavioral model of the system is constructed.Through the behavioral simulation,the normal operation of the circuit is verified,the noise transmission characteristics of each module is analyzed,and the method of determining the loop parameters are given.Finally,the phase error of the system is analyzed and calculated.(2)The designs of circuits of all the comprising functional modules including the phase detector,the operational amplifier,the low dropout regulator and the voltage controlled delay line are accomplished.The voltage controlled delay line adopts an AC-coupling complementary common-source stage cascaded with an inverter.A regulator is used as the control unit to adjust the delay time.In order to overcome the signal and duty-cycle distortion,an output buffer is added behind the voltage controlled delay line.(3)The operation of the system is verified by the full circuit simulation,and the system jitter performance at different PVT corners is calculated.The simulation results shows that the MDLL can operate within the frequency range from 10 GHz to 12 GHz.Under the condition of ideal inputs and supply,the root mean square value of jitter is less than 50.7fs.The peak to peak value of jitter is less than 674 fs.The consumption of current is no more than 16 m W.The phase error caused by mismatch is 1.17ps@3σ.(4)A self-calibration scheme is proposed to cancel the phase error induced by the phase detector and the operational amplifier.The calibration principle is described in detail.A framework to realize this scheme is constructed and verified by the behavioral simulation.The results show that the phase error is further reduced to 380fs@3σ.