RRAM-based Design Of In-memory Multiplication Accumulation Circuit And Logic Operation Circuit

With the in-depth research on the related technologies of Resistive Random Access Memory(RRAM).The characteristic that it can participate in calculation while saving data and the continuous improvement of its programming resistance accuracy make it widely studied in the integrated design scheme of storage and calculation.To bypass the strongest limitation affecting the traditional architecture,that is,the data transmission between memory and CPU,also known as von Neumann bottleneck.Taking neural network as a representative,the system that needs to process a large amount of data leads to the bottleneck becoming more and more prominent.In order to overcome this bottleneck in traditional Neural Networks,the hardware acceleration system of Binary Neural Network(BNN)based on RRAM has become an effective scheme.In this work,a hardware acceleration circuit design of Multiplication and Accumulation(MAC)operation in BNN based on RRAM array and a scheme of in-memory AND-Logic operation are proposed.MAC operation scheme is composed of parallel input circuit,storage array and cascaded current mirror circuit.XNOR logic between Weight and Activation function is realized on each 1-Transistor and 1-Resistor(1T1R)storage cell in the array.At the same time,the current in the effective cells are accumulated on the Bit Line(BL),and the current sum is mirrored in proportion through the cascaded current mirror circuit to convert the linear charge of the analog output capacitor into the output voltage.Compared with the structure of two cells realizing a single neural synapse,this scheme improves the utilization rate of memory resources by 50%,realizes the complete "+1" and "-1" XNOR operation in BNN and the accumulation operation of the same symbol results,ensures the calculation accuracy and improves the multiplication and accumulation operation speed.The cascaded current mirror circuit is introduced to clamp the BL voltage,so that the transistors in the unit work stably in the saturation region.The cumulative current sum on the BL is mirrored in proportion,which further improves the calculation accuracy,stability and linearity.It solves the problem of nonlinear drop of BL output voltage due to direct discharge of BL in traditional parallel computing mode.And innovatively reconstruct the reading circuit,parallel input circuit and storage array into a new memory AND-Logic operation circuit by reasonably configuring the control signal,which can realize the AND-Logic operation between data in multiple storage units in the same column.The basic Read-Write,AND-Logic and MAC functions of the designed RRAM in memory computing architecture are verified by simulation,and the factors affecting the resistance stability of the BL semi selected cell in the write operation are analyzed.The results show that the stability of mirror current from SL is 78.85% higher than that of BL with the same parallel input;The consistency of the results is improved by 68.2% by reducing the number of parallel inputs(from 64 bits to 32 bits).At 1.2V operating voltage,the highest frequency of inmemory and logical operations is about 476.19 MHz,and the calculated power consumption is about1.64 pJ.