Clock And Data Refovery Cirruit And Eye-opening Mornitor Circuit Design For 56 Gb/s PAM4 Reciever

The rapid development of big data,cloud computing and mobile networks require higher signal bandwidth and data transmission speed.When data rate is higher than 56 Gb/s,PAM4 is usually adopted in wireline transceiver.Due to the more jumps of PAM4 compared to NRZ,CDR in PAM4 system is more complicated.Moreover,frequency-dependent attenuation corrupts the signal integrity more severely as data rate increases.So,the EOM circuits are needed in highspeed wireline receivers to obtain an on-chip eyediagram to monitor the equalization results more precisely.Thus,the research on PAM4 CDR and EOM circuits is essential.This work presents a half-rate CDR circuit used in 56 Gb/s PAM4 wireline receivers,the frequency of recovered clock is 14 GHz.The circuit includes a half-rate bang-bang phase detector(PD),a V/I converter,a loop filter(LF)and a quadrature LC-QVCO.PD detects the phase error of local clock and received data and then transforms it into the lead/lag voltage signal.V/I converter converts voltage signals to current signals and feeds them into the LF.Current flows through LF,yielding poles and zeros in voltage domain to adjust the loop response.VCO use voltage signal of LF to adjust ossilation frequency to change the clock phase so that the clock and data are aligned.Also,an EOM used in PAM4 wireline receiver is presented.The circuit includes a dynamic comparator,a 6-bit DAC,a 6-bit phase interpolator(PI)and a digital controller.PI determines the abscissa of a pixel in the eye diagram,DAC determines the ordinate of a pixel,and dynamic comparator compares the magnitude of the output voltage of DAC and input signal.The results of comparator help to find the corresponding color of the pixel to draw the complete eyediagram.The digital control logic outputs the control word of PI and DAC,and stores the comparison results of comparator.PC compares the comparison results against a color map to obtain the eyediagram.This work presents the schematic design,layout and post-simulation of CDR in 65 nm CMOS technology.The chip area including pads is 0.399 mm2.Post simulation result under the worstcase suggests the total power consumption of CDR is 45.1 m W under 1.2 V supply,and the peakto-peak jitter of the recovered clock is 0.017 UI.The EOM is designed in 0.18 μm CMOS.The layout area is 0.042 mm2,and power consumption is 24.6 m W under 1.8 V supply.The resolution of EOM is 64×60 pixels,and color resolution of a single-pixel is 4-bit.The monitoring period of EOM is 76.8 μs,and the frequency of EOM is 400 MHz.Post simulation result suggests the EOM draws the full eyediagram correctly.The designed 14 GHz CDR and the EOM can be widely used in PAM4 wireline transceivers,and are valuable both theoretically and practically.