Research On Efficient Flipping Decoding Method For Flash Memory

Flash memory(Flash Memory),as a long-life and non-volatile data storage medium,has the advantages of large capacity,low power consumption,fast read and write,high-density storage and so on.NAND flash memory has obvious performance advantages in low-capacity applications that do not exceed 4GB by virtue of high-speed write and erase operations.More and more processors have direct NAND interface and can import data directly from NAND interface.In recent years,with the improvement of process technology and application requirements,the size of flash memory chips continues to shrink and the storage density continues to increase.The reliability of flash memory system is more and more affected by noise interference and other factors.The channel coding technologies of BCH code and LDPC code are applied to flash memory error control to improve the reliability of the storage system.However,the soft decision decoding algorithms based on soft information have high complexity and large processing delay.In order to further reduce the delay and hardware implementation complexity of the whole flash memory system,the efficient flipping decoding algorithms for BCH codes and LDPC codes are studied.First of all,introducing the type and structure,storage principle and error control mechanism of flash memory system,and introduces the codeword structure,representation method,coding and decoding principle around BCH codes and LDPC codes.Secondly,for binary LDPC codes,a variety of hard decision and soft-information-aided bit flipping decoding algorithms are introduced in detail,and a low latency hard decision bit flipping decoding algorithm with dynamic threshold is proposed.In the process of iterative decoding,the bit flipping threshold is automatically adjusted according to the bit flipping of the last decoding.In an iterative process,the reduction of the threshold makes as many error bits as possible to be flipped in parallel,which improves the effectiveness of decoding.The increase of the threshold prevents the overcorrection of correct bits and improves the reliability of decoding.The whole decoding process does not need to find the maximum flipping weight,which reduces the complexity and supports high-speed parallel decoding.Simulation results show that the bit flipping decoding method with dynamic threshold not only has low decoding complexity and fast convergence,but also has better decoding performance.The proposed efficient parallel bit flipping algorithm can be used as an important supplement to the soft decoding scheme.The flash memory system using LDPC codes can be combined with this algorithm to greatly reduce the call of the soft decision algorithms and effectively reduce the actual power consumption of the system.Then,studying the application of bit flipping decoding algorithms in BCH codes.Binary BCH codes have high parity check matrix density and great difference in row and column weight distribution,so it is necessary to transform the parity check matrix before bit flipping algorithm research.Firstly,sparse the BCH code according to the property that the generation matrix of the dual code of BCH code is the parity check matrix of the original code.Secondly,according to the cyclic structure of BCH codes,the distribution of sparse parity-check matrix of BCH codes is further regularized according to the cyclic structure of BCH codes.And finally the parity-check matrix equivalent to the original code is obtained with the minimum weight,and then the bit-flipping decoding algorithm is studied on the equivalent parity-check matrix.For some highperformance flash memory systems that use both BCH codes and LDPC codes,the bit flip decoding method we study can support the hardware implementation scheme of hard decision decoding of LDPC codes and BCH codes,and effectively reduce the resource overhead of the hardware system.Finally,for non-binary LDPC codes,to introduce the performance and decoding complexity of several symbol flipping decoding algorithms,and proposes a symbol flipping decoding algorithm which sets the maximum flipping symbol number hierarchically based on the number of iterations to realize the dynamic flipping of multiple symbols in each iteration.At the beginning of iteration,a large number of symbols are allowed to be flipped,which speeds up the speed of decoding convergence and reduces the decoding latency.With the increase of the number of iterations,the number of symbols allowed to be flipped at the same time decreases gradually,which can effectively correct the over flipped symbols and improve the flipping accuracy,so as to improve the decoding performance and system reliability.Simulation results show that,compared with the existing symbol flip decoding algorithms,the decoding method proposed in this paper can not only achieve better decoding performance,but also accelerate decoding convergence and reduce decoding latency.It is suitable for use in flash memory systems with high delay requirements.