Research And Implementation Of A Low-Power Secure Encryption SoC Based On 8-Bits MCU

With the increasing enhancement of information technology,the issue of information security becomes more and more prominent,and how to guarantee information security has become an issue that people must face.Data encryption is one of the important means to ensure information security,and its implementation includes software and hardware.Hardware encryption is widely adopted because of its advantages such as fast speed,low resource consumption and strong anti-attack capability.The objective of this paper is to implement a low-power secure encryption SoC based on an8-bit MCU,and after a comprehensive analysis of the performance,design cost and complexity requirements of the 8-bit MCU,the MC8051 processor is selected as the SoC core.The MC8051 processor was selected as the SoC core to design a low-power secure encryption SoC with multiple encryption algorithm integrated inside.The main work and innovations accomplished in this study are as follows:(1)Peripherals:The IP design of 40-bit encryption,48-bit encryption,DES-3DES encryption,AES encryption and watchdog modules based on the SFR bus protocol has been completed,which can be flexibly configured by software and has high configurability.To reduce the SoC area and SoC cost,the encryption algorithm modules are logically optimised:the logically optimised DES encryption and 3DES encryption are integrated into the DES-3DES encryption module;the logically optimised AES-128,AES-192 and AES-256 encryption and decryption algorithms are integrated into the AES encryption and decryption module.(2)Power consumption:Slow mode is added to reduce the dynamic power consumption of the SoC from the system level;clock gating is used to manage the clock of some modules to reduce the dynamic power consumption from the circuit level.After the addition of clock gating,the total power consumption of Normal mode is reduced by17.53%and the total power consumption of Slow mode is reduced by 21.53%,with the total power consumption of Slow mode accounting for only 1.03%of the power consumption of Normal mode.(3)Based on Keil-C51 and NC-Verilog,the design was verified at the module,subsystem and hardware/software system levels by means of functional and timing simulations.The hardware prototype verification of the design is completed based on the development board of ALTER EP4CE30 chip,and the correctness of the system function is verified from the hardware circuit level.(4)Based on the physical implementation flow of a standard digital circuit,the SMIC 180nm CMOS process was used to complete logic synthesis,formal verification,automatic layout and routing,and static timing analysis to convert the RTL of the secure encrypted SoC into a sign off standard GDS layout file.The final physical implementation of the secure SoC has a layout area of 1411.08×1249.92μm~2.