Design Of Readout Circuit For 64×64 Dual-mode Infrared Focal Plane Array

Infrared imaging technology has been widely used in many fields,such as meteorological monitoring,military guidance,security detection and so on.In order to adapt to more application scenarios,the focal plane readout circuit array is developing towards larger area,higher resolution and more mode integration.According to different imaging modes,the imaging system can be divided into active and passive modes.Passive imaging relies on the detection of the infrared radiation intensity of the target to complete 2D image rendering,which can reflect the contour of the measured target.Active imaging needs to be equipped with a specific optical radiation source to emit laser,detect the time when the laser is reflected back,obtain the photon flight time,and then measure the distance information of the target for 3D image rendering.The readout circuit designed in this paper has the above active and passive working modes.In the passive mode,it can ensure the dynamic range of light intensity detection by providing sufficient charge capacity;In the active mode,capacitor switching is used to realize the fast response to photocurrent in a wide dynamic range.In this paper,CTIA is used as the basic architecture of readout circuit,and a 64 × 64 dual-mode array,which can detect the light intensity information and distance information of the target at the same time in one frame.Aiming at the nonlinear error of TOF measurement caused by the change of light intensity in different environments,the measured light intensity data can be used to correct and realize accurate measurement.Aiming at the problem of introducing large routing parasitic capacitance into signal lines in large arrays,the slope push circuit and data transmission circuit are optimized to reduce the nonlinear error introduced in signal transmission.In addition,an enable control switch is designed for the bias circuit,which can flexibly control the working range of the circuit and greatly reduce the power consumption of the array.Based on the TSMC 0.18μm CMOS process,this paper has completed the pre-simulation and post-simulation verification of sequential logic circuits,ramp push circuits,data transmission circuit,bias circuit and 64×64 array readout circuit systems under 77 K temperature conditions.The frame rate of the array is 2.33 k Hz and the average power consumption is 157.9m W.Limited by server hardware resources,only 4×16 array readout circuit was verified by post-simulation.The simulation results showed that under the worst process angle,the ranging range of active mode is 200 ns,the ranging accuracy is 4ns,and the linearity of passive mode is 99.5%.