Design Of High Precision TDC Array System Based On GRO Built-in Clock

3D imaging technology based on direct time of flight(D-TOF)measurement is widely used in aerospace,biomedicine,precision guidance,terrain survey and other fields because of its advantages of fast detection speed,high sensitivity and strong anti-interference ability.Time to digital converter(TDC)is a special circuit system for D-TOF measurement,which can complete TOF quantization and transmission.In recent years,with the continuous development of 3D imaging technology,the requirements for measurement performance are higher and higher,which makes the research of TDC develop towards high precision,wide range,large scale and low power consumption.According to the design requirements of high-precision TOF quantization,on the basis of summarizing the TDC array system architecture,high-precision TDC pixel structure and its working principle,a GRO-TDC structure based on internal clock TDC architecture is proposed.In this structure,the high-frequency phase separation clock signal driving TDC is provided by the gated ring oscillator(GRO)built in the pixel,which avoids crosstalk caused by the longdistance routing of high-frequency phase separation clock in large-scale array and limits the improvement of system accuracy.GRO adopts a four stage ring oscillator structure based on the improved pseudo differential delay unit,which can output a 1.25 GHz clock signal.Combined with the two-stage TDC structure,the high segment is a 7bit counting TDC and the low segment is a 4bit interpolation TDC,which meets the requirements of 100 ps time resolution.Charge pump phase lock loop(CP-PLL)is used to provide control voltage for GRO.At the same time,GRO is closed-loop controlled to suppress the output clock frequency drift and maintain good PVT characteristics of the system.Based on the analysis of system power consumption,aiming at the application background of sparse photon event detection,event detection and inverted quantization timing are adopted to effectively reduce the system power consumption.Through the timing control circuit,output interface circuit,synchronization signal generation circuit and other data readout related modules,control the conversion between data quantization and data transmission mode,and assist in readout data.In this paper,based on TSMC 0.18μm standard CMOS process conditions and cadence circuit design platform,completed circuit design,layout design and simulation verification of1×16 TDC linear array system.The total area of the system layout is 2645.00μm×1552.50μm.Under the conditions of 27 ℃,1.8V power supply voltage,25 MHz reference clock,50 MHz transmission clock and 200 k Hz frame rate,the system and each module circuit function normally.The time resolution of TDC array is 100 ps,the measuring range is 102.4ns,the differential nonlinearity |DNL|≤0.40 LSB,the integral nonlinearity |INL|≤1.40 LSB,and the system power consumption is less than 155.97 m W,which basically meets the design index requirements.