Design Of Infrared Sensing Readout Circuit Based On Inverted Quantitative Timing

The infrared sensing ranging imaging technology based on Single Photon Avalanche Diode(SPAD)which can measure the Time-of-Flight(TOF)by actively emitting infrared laser,calculating the time from laser emission to SPAD receiving the photons reflected by the target,and finally achieves three-dimensional imaging of the target.The infrared single-photon detection technology is widely used in medical imaging,face recognition and lidar fields by actively ranging imaging.It is developing continuous in the direction of high performance such as large array scale,and the performance requirements of the readout circuit are getting higher and higher,which leads to the problem of power consumption becoming one of the main reasons for limiting the scale expansion of the SPAD array.Therefore,this paper will focus on the design of low-power readout circuits.This paper is based on the low-power requirements and large array scale in sparse photonic application scenarios,analyzes the power consumption sources from two working stages of the Read-Out Integrated Circuit(ROIC)— quantization and data transmission,and completes the low-power ROIC design based on inverted quantitative timing.The quantitative timing in this paper adopts the inverted quantization timing.The Time-to-Digital Converter(TDC)inside the pixel will quantify the time interval complementary to the TOF.That is,the event that the pixel detects a photon is used as the condition to start the TDC inside the pixel.Compared to the classical ROIC systems,the quantization timing in this paper can reduce the quantization power consumption of ROIC systems by reducing the number of TDCs operating in the array.Since the time of photons arriving at the detector array is usually scattered,under the quantization timing in this paper,the TDCs inside the array will be started in time division,which can reduce the transient power consumption of the system.A pseudo-three-segment TDC matching this timing is designed to reduce the power consumption of the pixel TDC by reducing the number of TDC bits driven by the high-frequency clock.In addition,aiming at the problem of excessive data transmission in the classic ROIC system,this paper designs a circuit scheme that only transmits effective quantized data,which greatly reduces the data transmission volume of the system and relieves the data transmission pressure of large arrays.Aiming at the problem that the data generated by this scheme can’t be located,an additional 1-bit auxiliary coded data is used for each pixel to determine the array position of the quantitative data.The accurate positioning of the effective quantized data can be achieved with a small data cost.Based on TSMC 0.18μm 1P6 M CMOS process conditions,the schematic and layout design of the low-power 8×8 array readout circuit system proposed in this paper,and the simulation verification as well as the tape-out work were completed.The final layout area of the system is 2500μm×1925μm.The simulation results show that under the conditions of 1.8/5V power supply voltage,27℃ operating temperature,100 k Hz data acquisition frame rate,50 MHz data readout clock,and 250 MHz four high-frequency split-phase quantization reference clock driving,the ROIC designed in this paper functions normally,it can realize the complete process of photon detection,time quantization and efficient quantitative data transmission with up to 4pixels per row of array.The ROIC’s time quantification function is normal,it can obtain a time resolution of 500 ps,a timing range of 2μs,the maximum differential nonlinearity is 0.356 LSB,the maximum integral nonlinearity is 0.908 LSB,and the average system power consumption is14.83 m W.The simulation results basically meet the design requirements.